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? 2007 microchip technology inc. ds41268d pic12f510/16f506 data sheet 8/14-pin, 8-bit flash microcontrollers
ds41268d-page ii ? 2007 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip tec hnology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are tr ademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2007 microchip technology inc. ds41268d-page 1 pic12f510/16f506 devices included in this data sheet: ?pic16f506 ?pic12f510 high-performance risc cpu: ? only 33 single-word instructions to learn ? all single-cycle instructions except for program branches, which are two-cycle ? 12-bit wide instructions ? two-level deep hardware stack ? direct, indirect and relative addressing modes for data and instructions ? 8-bit wide data path ? 10 special function hardware registers (pic12f510) ? 13 special function hardware registers (pic16f506) ? operating speed: - dc ? 8 mhz crystal oscillator (pic12f510) - dc ? 500 ns instruction cycle (pic12f510) - dc ? 20 mhz crystal oscillator (pic16f506) - dc ? 200 ns instruction cycle (pic16f506) special microcontroller features: ? 4 or 8 mhz selectable precision internal oscillator: - factory calibrated to 1% ? in-circuit serial programming? (icsp?) ? in-circuit debugging (icd) support ? power-on reset (por) ? device reset timer (drt): - short drt (1.125 ms, typical) for intosc, extrc and ec - drt (18 ms, typical) for hs, xt and lp ? watchdog timer (wdt) with dedicated on-chip rc oscillator for reliable operation ? programmable code protection ? multiplexed mclr input pin ? selectable internal weak pull-ups on i/o pins ? power-saving sleep mode ? wake-up from sleep on pin change ? wake-up from sleep on comparator change ? selectable oscillator options: - intosc: 4/8 mhz precision internal oscillator - extrc: external low-cost rc oscillator - xt: standard crystal/resonator - lp: power-saving, low-frequency crystal - hs: high-speed crystal/resonator (pic16f506 only) - ec: high-speed external clock input (pic16f506 only) ? analog-to-digital (a/d) converter: - 8-bit resolution - 4-input channels (1 channel is dedicated to conversion of the internal 0.6v absolute voltage reference) ? high current sink/source for direct led drive ? 8-bit real-time clock/counter (tmr0) with 8-bit programmable prescaler low-power features/cmos technology: ? operating current: -< 175 a @ 2v, 4 mhz, typical ? standby current: - 100 na @ 2v, typical ? low-power, high-speed flash technology: - 100,000 cycle flash endurance - > 40-year retention ? fully static design ? wide operating voltage range: 2.0v to 5.5v ? wide temperature range: - industrial: -40 c to +85 c - extended: -40 c to +125 c peripheral features (pic12f510): ? 6 i/o pins: - 5 i/o pins with individual direction control - 1 input only pin ? 1 analog comparator with absolute reference peripheral features (pic16f506): ? 12 i/o pins: - 11 i/o pins with individual direction control - 1 input only pin ? 2 analog comparators with absolute reference and programmable reference 8/14-pin, 8-bit flas h microcontroller
pic12f510/16f506 ds41268d-page 2 ? 2007 microchip technology inc. pin diagrams device program memory data memory i/o timers 8-bit flash (words) sram (bytes) pic16f506 1024 67 12 1 pic12f510 1024 38 6 1 pdip, soic, msop v dd rb5/osc1/clkin rb4/osc2/clkout rb3/mclr /v pp rc5/t0cki rc4/c2out rc3 v ss rb0/an0/c1in+/icspdat rb1/an1/c1in-/icspclk rb2/an2/c1out rc0/c2in+ rc1/c2in- rc2/cv ref pic16f506 pdip, soic and tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v dd gp5/osc1/clkin gp4/osc2 gp3/mclr /v pp v ss gp0/an0/c1in+/icspdat gp1/an1/c1in-/icspclk gp2/an2/t0cki/c1out pic12f510 1 2 3 4 5 6 7 8 dfn pic12f510 1 2 3 4 8 7 6 5 v ss gp0/an0/c1in+/icspdat gp1/an1/c1in-/icspclk gp2/an2/t0cki/c1outi v dd gp5/osc1/clkin gp4/osc2 gp3/mclr /v pp
? 2007 microchip technology inc. ds41268d-page 3 pic12f510/16f506 table of contents 1.0 general description......................................................................................................... ............................................................. 5 2.0 pic12f510/16f506 device varieties .......................................................................................... ................................................ 7 3.0 architectural overview ...................................................................................................... ........................................................... 9 4.0 memory organization ......................................................................................................... ........................................................ 15 5.0 i/o port .................................................................................................................... ................................................................... 27 6.0 tmr0 module and tmr0 register............................................................................................... .............................................. 39 7.0 comparator(s) ............................................................................................................... ............................................................. 43 8.0 comparator voltage reference module (pic16f506 only)........................................................................ ................................ 49 9.0 analog-to-digital (a/d) converter........................................................................................... .................................................... 51 10.0 special features of the cpu................................................................................................ .................................................... 55 11.0 instruction set summary .................................................................................................... ........................................................ 71 12.0 development support........................................................................................................ ......................................................... 79 13.0 electrical characteristics ................................................................................................. ........................................................... 83 14.0 dc and ac characteristics graphs and charts ................................................................................ ......................................... 97 15.0 packaging.................................................................................................................. ............................................................... 105 index .......................................................................................................................... ........................................................................ 117 the microchip web site ......................................................................................................... ............................................................ 119 customer change notification service ........................................................................................... ................................................... 119 customer support............................................................................................................... ............................................................... 119 reader response ................................................................................................................ .............................................................. 120 product identification system .................................................................................................. .......................................................... 121 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
pic12f510/16f506 ds41268d-page 4 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds41268d.-page 5 pic12f510/16f506 1.0 general description the pic12f510/16f506 devices from microchip technology are low-cost, high-performance, 8-bit, fully- static, flash-based cmos microcontrollers. they employ a risc architecture with only 33 single-word/ single-cycle instructions. all instructions are single- cycle except for program branches, which take two cycles. the pic12f510/16f506 devices deliver performance in an order of magnitude higher than their competitors in the same price category. the 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. the easy-to-use and easy- to-remember instruction set reduces development time significantly. the pic12f510/16f506 products are equipped with special features that reduce system cost and power requirements. the power-on reset (por) and device reset timer (drt) eliminate the need for external reset circuitry. there are four oscillator con- figurations to choose from (six on the pic16f506), including intosc internal oscillator mode and the power-saving lp (low-power) oscillator mode. power-saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the pic12f510/16f506 devices allow the customer to take full advantage of microchip?s price leadership in flash programmable microcontrollers, while benefiting from the flash programmable flexibility. the pic12f510/16f506 products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ?c? compiler, a low-cost development programmer and a full featured program- mer. all the tools are supported on ibm ? pc and compatible machines. 1.1 applications the pic12f510/16f506 devices fit in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. the flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and conve- nient. the small footprint packages, for through hole or surface mounting, make these microcontrollers perfect for applications with space limitations. low-cost, low- power, high-performance, ease-of-use and i/o flexibil- ity make the pic12f510/16f506 devices very versa- tile, even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and plds in larger systems and coprocessor applications). table 1-1: pic12f510/16f506 devices pic16f506 pic12f510 clock maximum frequency of operation (mhz) 20 8 memory flash program memory (words) 1024 1024 data memory (bytes) 67 38 peripherals timer module(s) tmr0 tmr0 wake-up from sleep on pin change yes yes features i/o pins 11 5 input only pin 1 1 internal pull-ups yes yes in-circuit serial programming yes yes number of instructions 33 33 packages 14-pin pdip, soic, tssop 8-pin pdip, soic, msop, dfn the pic12f510/16f506 devices have power-on reset, selectable watchdog timer, selectable code-protect, high i/o current capability and precision internal oscillator. the pic12f510/16f506 devices use serial programmi ng with data pin rb0/gp0 and clock pin rb1/gp1.
pic12f510/16f506 ds41268d.-page 6 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds41268d-page 7 pic12f510/16f506 2.0 pic12f510/16f506 device varieties a variety of packaging options are available. depend- ing on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic12f510/16f506 product identification system at the back of this data sheet to specify the correct part number. 2.1 quick turn programming (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. the devices are identical to the flash devices, but with all flash locations and fuse options already programmed by the factory. certain code and prototype verification procedures do apply before production shipments are available. please contact your local microchip technology sales office for more details. 2.2 serialized quick turn programming sm (sqtp sm ) devices microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number, which can serve as an entry code, password or id number.
pic12f510/16f506 ds41268d-page 8 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds41268d-page 9 pic12f510/16f506 3.0 architectural overview the high performance of the pic12f510/16f506 devices can be attributed to a number of architectural features commonly found in risc microprocessors. the pic12f510/16f506 devices use a harvard archi- tecture in which program and data are accessed on separate buses. this improves bandwidth over tradi- tional von neumann architectures where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. a 12-bit wide program mem- ory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execu- tion of instructions. consequently, all instructions (33) execute in a single cycle (200 ns @ 20 mhz, 1 s @ 4 mhz) except for program branches. table 3-1 lists program memory (flash) and data memory (ram) for the pic12f510/16f506 devices. table 3-1: pic12f510/16f506 memory the pic12f510/16f506 devices can directly or indi- rectly address its register files and data memory. all special function registers (sfrs), including the pc, are mapped in the data memory. the pic12f510/ 16f506 devices have a highly orthogonal (symmetri- cal) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. this symmetrical nature and lack of ?special optimal situations? make programming with the pic12f510/16f506 devices simple, yet efficient. in addition, the learning curve is reduced significantly. the pic12f510/16f506 devices contain an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8 bits wide and capable of addition, subtrac- tion, shift and logical operations. unless otherwise mentioned, arithmetic operations are two?s comple- ment in nature. in two-operand instructions, one operand is typically the w (working) register. the other operand is either a file register or an immediate constant. in single-operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc) and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respec- tively, in subtraction. see the subwf and addwf instructions for examples. a simplified block diagram is shown in figure 3-1 for pic12f510 with the corresponding device pins described in table 3-2. a simplified block diagram for pic16f506 is shown in figure 3-2 with the corresponding device pins described in table 3-3. device memory program data pic12f510 1024 x 12 38 x 8 pic16f506 1024 x 12 67 x 8
pic12f510/16f506 ds41268d-page 10 ? 2007 microchip technology inc. figure 3-1: pic12f510 series block diagram flash program memory 10-11 data bus 8 12 program bus instruction reg program counter ram file registers direct addr 5 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg device reset power-on reset watchdog timer instruction decode & control timing generation osc1/clkin mclr v dd , v ss timer0 gpio 8 8 gp4 gp3 gp2 gp1/icspclk gp0/icspdat 5-7 3 gp5 stack 1 stack 2 internal rc clock 1k x 12 38 bytes timer comparator 8-bit adc c1in+ c1in- c1out an0 an1 an2 cv ref osc2 t0cki
? 2007 microchip technology inc. ds41268d-page 11 pic12f510/16f506 table 3-2: pin descriptions ? pic12f510 name i/o/p type input type output type description gp0/an0/c1in+/icspdat gp0 ttl cmos bidirectional i/o port. can be software pro- grammed for internal weak pull-up and wake-up from sleep on pin change. an0 an ? adc channel input. c1in+ an ? comparator input. icspdat st cmos in-circuit serial programming data pin. gp1/an1/c1in-/icspclk gp1 ttl cmos bidirectional i/o port. can be software pro- grammed for internal weak pull-up and wake-up from sleep on pin change. an1 an ? adc channel input. c1in- an ? comparator input. icspclk st ? in-circuit serial programming clock pin. gp2/an2/t0cki/c1out gp2 ttl cmos bidirectional i/o port. an2 an ? adc channel input. t0cki st ? timer0 clock input. c1out ? cmos comparator output. gp3/mclr/ v pp gp3 ttl ? standard ttl input. can be software pro- grammed for internal weak pull-up and wake-up from sleep on pin change. mclr st ? mclr input ? weak pull-up always enabled in this mode. v pp hv ? programming voltage input. gp4/osc2 gp4 ttl cmos bidirectional i/o port. osc2 ? xtal xtal oscillator output pin. gp5/osc1/clkin gp5 ttl cmos bidirectional i/o port. osc1 xtal ? xtal oscillator input pin. clkin st ? extrc schmitt trigger input. v dd v dd p ? positive supply for logic and i/o pins. v ss v ss p ? ground reference for logic and i/o pins. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input, an = analog voltage, hv = high voltage
pic12f510/16f506 ds41268d-page 12 ? 2007 microchip technology inc. figure 3-2: pic16f506 series block diagram flash program memory 10 data bus 8 10 program bus instruction reg program counter ram file registers direct addr 5 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg device reset power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss timer0 portb 8 8 rb4 rb3 rb2 rb1/icspclk rb0/icspdat 5-7 3 rb5 stack 1 stack 2 internal rc clock 1k x 12 67 bytes timer portc rc4 rc3 rc2 rc1 rc0 rc5 comparator 2 c1in+ c1in- c1out c2in+ c2in- c2out an0 an1 an2 8-bit adc cv ref cv ref cv ref comparator 1 0.6v reference t0cki
? 2007 microchip technology inc. ds41268d-page 13 pic12f510/16f506 table 3-3: pin descriptions ? pic16f506 name function input type output type description rb0/an0/c1in+/icspdat rb0 ttl cmos bidirectional i/o port. can be software pro- grammed for internal weak pull-up and wake-up from sleep on pin change. an0 an ? adc channel input. c1in+ an ? comparator 1 input. icspdat st cmos in-circuit serial programming data pin. rb1/an1/c1in-/icspclk rb1 ttl cmos bidirectional i/o port. can be software pro- grammed for internal weak pull-up and wake-up from sleep on pin change. an1 an ? adc channel input. c1in- an ? comparator 1 input. icspclk st ? in-circuit serial programming clock pin. rb2/an2/c1out rb2 ttl cmos bidirectional i/o port. an2 an ? adc channel input. c1out ? cmos comparator 1 output. rb3/mclr /v pp rb3 ttl ? standard ttl input. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. mclr st ? mclr input ? weak pull-up always enabled in this mode. v pp hv ? programming voltage input. rb4/osc2/clkout rb4 ttl cmos bidirectional i/o port. can be software pro- grammed for internal weak pull-up and wake-up from sleep on pin change. osc2 ? xtal xtal oscillator output pin. clkout ? cmos extrc/intosc clkout pin (f osc /4). rb5/osc1/clkin rb5 ttl cmos bidirectional i/o port. osc1 xtal ? xtal oscillator input pin. clkin st ? extrc/ec schmitt trigger input. rc0/c2in+ rc0 ttl cmos bidirectional i/o port. c2in+ an ? comparator 2 input. rc1/c2in- rc1 ttl cmos bidirectional i/o port. c2in- an ? comparator 2 input. rc2/cv ref rc2 ttl cmos bidirectional i/o port. cv ref ? an programmable voltage reference output. rc3 rc3 ttl cmos bidirectional i/o port. rc4/c2out rc4 ttl cmos bidirectional i/o port. c2out ? cmos comparator 2 output. rc5/t0cki rc5 ttl cmos bidirectional i/o port. t0cki st ? timer0 clock input. v dd v dd p ? positive supply for logic and i/o pins. v ss v ss p ? ground reference for logic and i/o pins. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input, an = analog voltage, hv = high voltage
pic12f510/16f506 ds41268d-page 14 ? 2007 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pc is incremented every q1 and the instruction is fetched from program memory and latched into the instruction register in q4. it is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-3 and example 3-1. 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the pc to change (e.g., goto ), then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the pc incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-3: clock /instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc pc pc + 1 pc + 2 fetch inst (pc) execute inst (pc ? 1) fetch inst (pc + 1) execute inst (pc) fetch inst (pc + 2) execute inst (pc + 1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. 1. movlw 03h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf portb, bit1 fetch 4 flush fetch sub_1 execute sub_1
? 2007 microchip technology inc. ds41268d-page 15 pic12f510/16f506 4.0 memory organization the pic12f510/16f506 memories are organized into program memory and data memory. for devices with more than 512 bytes of program memory, a paging scheme is used. program memory pages are accessed using status register bit pa0. for the pic12f510 and pic16f506, with data memory register files of more than 32 registers, a banking scheme is used. data memory banks are accessed using the file select register (fsr). 4.1 program memory organization for the pic12f510/16f506 the pic12f510/16f506 devices have a 10-bit program counter (pc) capable of addressing a 2k x 12 program memory space. only the first 1k x 12 (0000h-03ffh) are physically implemented (see figure 4-1). accessing a location above these boundaries will cause a wraparound within the 1k x 12 space. the effective reset vector is a 0000h (see figure 4-1). location 03ffh contains the internal clock oscillator calibration value. this value should never be overwritten. figure 4-1: program memory map and stack for the pic12f510/16f506 call , retlw pc<11:0> stack level 1 stack level 2 user memory space 10 0000h 7ffh 01ffh 0200h on-chip program memory reset vector (1) note 1: address 0000h becomes the effective reset vector. location 03ffh contains the movlw xx internal oscillator calibration value. 512 word 1024 word 03ffh 0400h on-chip program memory
pic12f510/16f506 ds41268d-page 16 ? 2007 microchip technology inc. 4.2 data memory organization data memory is composed of registers or bytes of ram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers (sfrs) and general purpose registers (gprs). the special function registers include the tmr0 register, the program counter (pcl), the status register, the i/o registers (ports) and the file select register (fsr). in addition, special function registers are used to control the i/o port configuration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic12f510, the register file is composed of 10 special function registers, 6 general purpose registers and 32 general purpose registers accessed by banking (see figure 4-2). for the pic16f506, the register file is composed of 13 special function registers, 3 general purpose registers and 64 general purpose registers, accessed by banking (see figure 4-3). 4.2.1 general purpose register file the general purpose register file is accessed either directly or indirectly through the file select register (fsr). see section 4.8 ?indirect data addressing: indf and fsr registers? . figure 4-2: pic12f510 register file map figure 4-3: pic16f506 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal gpio 0fh 10h bank 0 bank 1 3fh 30h 20h general purpose registers general purpose registers general purpose registers 08h addresses map back to addresses in bank 0. note 1: not a physical register. fsr<5> 0 1 cm1con0 2fh 09h 0ah adcon0 adres file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal portb 10h bank 0 bank 1 bank 2 bank 3 3fh 30h 20h 5fh 50h 40h 7fh 70h 60h general purpose registers general purpose registers general purpose registers general purpose registers general purpose registers portc 08h addresses map back to addresses in bank 0. note 1: not a physical register. fsr<6:5> 00 01 10 11 2fh 4fh 6fh 0dh cm1con0 cm2con0 vrcon 09h 0ah 0bh adres adcon0 0ch 0fh
? 2007 microchip technology inc. ds41268d-page 17 pic12f510/16f506 4.2.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral functions to control the operation of the device (see table 4-1). the special function registers can be classified into two sets. the special function registers associated with the ?core? functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. table 4-1: special function re gister summary ? pic12f510 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset n/a tris i/o control registers (trisgpio) --11 1111 n/a option contains control bits to configure timer0 and timer0/wdt prescaler 1111 1111 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx 01h tmr0 timer0 module register xxxx xxxx 02h (1) pcl low order 8 bits of pc 1111 1111 03h status gpwuf cwuf pa0 to pd zdcc 0001 1xxx 04h fsr indirect data memory address pointer 110x xxxx 05h osccal cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? 1111 111- 06h gpio ? ? gp5 gp4 gp3 gp2 gp1 gp0 --xx xxxx 07h cm1con0 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 1111 1111 08h adcon0 ans1 ans0 adcs1 adcs0 chs1 chs0 go/done adon 1111 1100 09h adres adc conversion result xxxx xxxx legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ? (if applicable). shaded cells = unimplemented or unused. note 1: the upper byte of the program counter is not directly accessible. see section 4.6 ?program counter? for an explanation of how to access these bits.
pic12f510/16f506 ds41268d-page 18 ? 2007 microchip technology inc. table 4-2: special function re gister summary ? pic16f506 4.3 status register this register contains the arithmetic status of the alu, the reset status and the page preselect bit. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status , will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). therefore, it is recommended that only bcf , bsf and movwf instructions be used to alter the status regis- ter. these instructions do not affect the z, dc or c bits from the status register. for other instructions which do affect status bits, see section 11.0 ?instruction set summary? . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset n/a tris i/o control registers (trisb, trisc) --11 1111 n/a option contains control bits to configure timer0 and timer0/wdt prescaler 1111 1111 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx 01h tmr0 timer0 module register xxxx xxxx 02h (1) pcl low order 8 bits of pc 1111 1111 03h status rbwuf cwuf pa0 to pd zdcc 0001 1xxx 04h fsr indirect data memory address pointer 100x xxxx 05h osccal cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? 1111 111- 06h portb ? ? rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx 07h portc ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx 08h cm1con0 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 1111 1111 09h adcon0 ans1 ans0 adcs1 adcs0 chs1 chs0 go/done adon 1111 1100 0ah adres adc conversion result xxxx xxxx 0bh cm2con0 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu 1111 1111 0ch vrcon vren vroe vrr ? (2) vr3 vr2 vr1 vr0 0011 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ? (if applicable). shaded cells = unimplemented or unused. note 1: the upper byte of the program counter is not directly accessible. see section 4.6 ?program counter? for an explanation of how to access these bits. 2: unimplemented bit vrcon<4> read as ? 1 ?.
? 2007 microchip technology inc. ds41268d-page 19 pic12f510/16f506 register 4-1: status: status register (pic12f510) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x gpwuf cwuf pa0 to pd zdcc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gpwuf : gpio reset bit 1 = reset due to wake-up from sleep on pin change 0 = after power-up or other reset bit 6 cwuf : comparator reset bit 1 = reset due to wake-up from sleep on comparator change 0 = after power-up or other reset bit 5 pa0 : program page preselect bit 1 = page 1 (200h-3ffh) 0 = page 0 (000h-1ffh) each page is 512 bytes. using the pa0 bit as a general purpose read/write bit in dev ices which do not use it fo r program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit (for addwf and subwf instructions) addwf: 1 = a carry from the 4th low-order bit of the result occurred 0 = a carry from the 4th low-order bit of the result did not occur subwf: 1 = a borrow from the 4th low-order bit of the result did not occur 0 = a borrow from the 4th low-order bit of the result occurred bit 0 c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf: subwf: rrf or rlf: 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred
pic12f510/16f506 ds41268d-page 20 ? 2007 microchip technology inc. register 4-2: status: status register (pic16f506) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x rbwuf cwuf pa0 to pd zdcc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbwuf : portb reset bit 1 = reset due to wake-up from sleep on pin change 0 = after power-up or other reset bit 6 cwuf : comparator reset bit 1 = reset due to wake-up from sleep on comparator change 0 = after power-up or other reset bit 5 pa0 : program page preselect bit 1 = page 1 (200h-3ffh) 0 = page 0 (000h-1ffh) each page is 512 bytes. using the pa0 bit as a general purpose read/write bit in dev ices which do not use it fo r program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit (for addwf and subwf instructions) addwf: 1 = a carry from the 4th low-order bit of the result occurred 0 = a carry from the 4th low-order bit of the result did not occur subwf: 1 = a borrow from the 4th low-order bit of the result did not occur 0 = a borrow from the 4th low-order bit of the result occurred bit 0 c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf: subwf: rrf or rlf: 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred
? 2007 microchip technology inc. ds41268d-page 21 pic12f510/16f506 4.4 option register the option register is a 8-bit wide, write-only register, that contains various control bits to configure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option register. a reset sets the option<7:0> bits. note 1: if tris bit is set to ? 0 ?, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that tris overrides option control of gppu /rbpu and gpwu /rbwu ). 2: if the t0cs bit is set to ? 1 ?, it will override the tris function on the t0cki pin. register 4-3: option_reg: option register (pic12f510) w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 gpwu gppu t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gpwu : enable wake-up on pin change bit (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 6 gppu : enable weak pull-ups bit (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 5 t0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
pic12f510/16f506 ds41268d-page 22 ? 2007 microchip technology inc. register 4-4: option_reg: option register (pic16f506) w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 rbwu rbpu t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbwu : enable wake-up on pin change bit (rb0, rb1, rb3, rb4) 1 = disabled 0 = enabled bit 6 rbpu : enable weak pull-ups bit (rb0, rb1, rb3, rb4) 1 = disabled 0 = enabled bit 5 t0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
? 2007 microchip technology inc. ds41268d-page 23 pic12f510/16f506 4.5 osccal register the oscillator calibration (osccal) register is used to calibrate the internal precision 4/8 mhz oscillator. it contains seven bits for calibration . after you move in the calibration constant, do not change the value. see section 10.2.5 ?internal 4/8 mhz rc oscillator? . note: erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. register 4-5: osccal: osci llator calibration register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u-0 cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 cal<6:0> : oscillator calibration bits 0111111 = maximum frequency ? ? ? 0000001 0000000 = center frequency 1111111 ? ? ? 1000000 = minimum frequency bit 0 unimplemented : read as ? 0 ?
pic12f510/16f506 ds41268d-page 24 ? 2007 microchip technology inc. 4.6 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next program instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the program counter (pcl) is mapped to pc<7:0>. bit 5 of the status register provides page information to bit 9 of the pc (figure 4-4). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc again are provided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-4). instructions where the pcl is the destination or modify pcl instructions include movwf pc , addwf pc and bsf pc , 5. figure 4-4: loading of pc branch instructions 4.6.1 effects of reset the pc is set upon a reset, which means that the pc addresses the last location in the last page (i.e., the oscillator calibration instruction). after executing movlw xx , the pc will roll over to location 00h and begin executing user code. the status register page preselect bits are cleared upon a reset, which means that page 0 is preselected. therefore, upon a reset, a goto instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 4.7 stack the pic12f510/16f506 devices have a two-deep, 12-bit wide hardware push/pop stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current pc value, incremented by one, into stack level 1. if more than two sequential call s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the pc and then copy stack level 2 contents into stack level 1. if more than two sequential retlw s are executed, the stack will be filled with the address previously stored in stack level 2. note: because pc<8> is cleared in the call instruction or any modify pcl instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). pa0 status pc 87 0 pcl 9 instruction word 70 goto instruction call or modify pcl instruction pa0 status pc 87 0 pcl 9 instruction word 70 reset to ? 0 ? note 1: the w register will be loaded with the lit- eral value specified in the instruction. this is particularly useful for the implementa- tion of data look-up tables within the program memory. 2: there are no status bits to indicate stack overflows or stack underflow conditions. 3: there are no instruction mnemonics called push or pop. these are actions that occur from the execution of the call and retlw instructions.
? 2007 microchip technology inc. ds41268d-page 25 pic12f510/16f506 4.8 indirect data addressing: indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. 4.8.1 indirect addressing example ? register file 07 contains the value 10h ? register file 08 contains the value 0ah ? load the value 07 into the fsr register ? a read of the indf register will return the value of 10h ? increment the value of the fsr register by one (fsr = 08) ? a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0 ) will produce 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-1. example 4-1: how to clear ram using indirect addressing the fsr is a 5-bit wide register. it is used in conjunc- tion with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. figure 4-5: direct/indirect addressing (pic12f510) pic16f506 ? uses fsr<6:5>. selects from bank 0 to bank 3. fsr<7> is unimplemented, read as ? 1 ?. pic12f510 ? uses fsr<5>. selects from bank 0 to bank 1. fsr<7:6> are unimplemented, read as ? 11 ?. movlw 0x10 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue : note 1: for register map detail, see figure 4-2. 2: grey boxes are unimplemented and read as ? 1 ?. bank select location select location select bank select indirect addressing direct addressing data memory (1) 0fh 10h bank 0 bank 1 0 4 5 6 (fsr) 00 01 00h 1fh 3fh (opcode) 0 4 5 6 (fsr) addresses map back to addresses in bank 0. 3 2 1 321
pic12f510/16f506 ds41268d-page 26 ? 2007 microchip technology inc. figure 4-6: direct/indirect addressing (pic16f506) note 1: for register map detail, see figure 4-3. direct addressing (fsr) bank select location select 00h 0fh 10h data memory (1) 1fh 3fh 5fh 7fh indirect addressing bank location select addresses map back to addresses in bank 0. 65 43210 (opcode) 6 543210 (fsr) 00 01 10 11 bank 0 bank 1 bank 2 bank 3
? 2007 microchip technology inc. ds41268d-page 27 pic12f510/16f506 5.0 i/o port as with any other register, the i/o register(s) can be written and read under program control. however, read instructions (e.g., movf portb , w ) always read the i/o pins independent of the pin?s input/output modes. on reset, all i/o ports are defined as input (inputs are at high-impedance) since the i/o control registers are all set. 5.1 portb/gpio portb/gpio is an 8-bit i/o register. only the low- order 6 bits are used (rb/gp<5:0>). bits 7 and 6 are unimplemented and read as ? 0 ?s. please note that rb3/ gp3 is an input only pin. the configuration word can set several i/o?s to alternate functions. when acting as alternate functions, the pins will read as ? 0 ? during a port read. pins rb0/gp0, rb1/gp1, rb3/gp3 and rb4 (pic16f506 only) can be configured with weak pull-up and also for wake-up on change. the wake-up on change and weak pull-up functions are not pin select- able. if rb3/gp3/mclr is configured as mclr , weak pull-up is always on and wake-up on change for this pin is not enabled. 5.2 portc (pic16f506 only) portc is an 8-bit i/o register. only the low-order 6 bits are used (rc<5:0>). bits 7 and 6 are unimplemented and read as ? 0 ?s. 5.3 tris registers the output driver control register is loaded with the contents of the w register by executing the tris f instruction. a ? 1 ? from a tris register bit puts the corre- sponding output driver in a high-impedance mode. a ? 0 ? puts the contents of the output data latch on the selected pins, enabling the output buffer. the exception is rb3/gp3, which are input only, and the t0cki pin, which may be controlled by the option register. see register 4-3. 5.4 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 5-1. all port pins, except rb3/gp3 which is input only, may be used for both input and output oper- ations. for input operations, these ports are non-latch- ing. any input must be present until read by an input instruction (e.g., movf portb , w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the correspond- ing direction control bit in tris must be cleared (= 0 ). for use as an input, the corresponding tris bit must be set. any i/o pin (except rb3/gp3) can be programmed individually as input or output. figure 5-1: pic12f510/16f506 equivalent circuit for pin drive (2) note: on the pic12f510, i/o portb is refer- enced as gpio. on the pic16f506, i/o portb is referenced as portb. note: a read of the port reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high but the external system is holding it low, a read of the port will indicate that the pin is low. note: the tris registers are write-only and are set (output drivers disabled) upon reset. data bus q d q ck p n interface data v ss v dd i/o pin bus reset note 1: gp3/rb3 has protection diode to v ss only. 2: for pin specific information, see figure 5-2 through figure 5-13. v ss v dd (1)
pic12f510/16f506 ds41268d-page 28 ? 2007 microchip technology inc. figure 5-2: blo ck diagram of gp0/rb0 and gp1/rb1 figure 5-3: block diagram of gp3/rb3 (with weak pull-up and wake-up on change) data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . d ck q mismatch rbpu gppu adc pin ebl comp pin ebl adc comp i/o pin (1) data bus rd port note 1: gp3/mclr pin has a protection diode to v ss only. gppu d ck q mismatch mclre rbpu reset i/o pin (1)
? 2007 microchip technology inc. ds41268d-page 29 pic12f510/16f506 figure 5-4: block diagram of gp2 figure 5-5: block diagram of rb2 data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 0 1 t0cs c1t0cs c1outen adc c1out adc pin enable i/o pin (1) t0cki data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 0 1 c1outen adc c1out adc pin enable i/o pin (1)
pic12f510/16f506 ds41268d-page 30 ? 2007 microchip technology inc. figure 5-6: block diagram of rb4 figure 5-7: block diagram of gp4 data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 2: input mode is disabled when pin is used for oscillator. 1 0 intosc/rc/ec clkout enable f osc /4 oscillator circuit osc1 rbpu i/o pin (1) (note 2) data bus q d q ck q d q ck wr port tris ?f? data tris rd port i/o pin (1) w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . intosc/rc oscillator circuit osc1
? 2007 microchip technology inc. ds41268d-page 31 pic12f510/16f506 figure 5-8: blo ck diagram of rb5/gp5 figure 5-9: block diagram of rc0/rc1 data bus q d q ck q d q ck wr port tris ?f? data tris rd port i/o pin (1) w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 2: input mode is disabled when pin is used for oscillator. oscillator circuit osc2 (note 2) data bus q d q ck q d q ck wr port tris ?f? data tris rd port i/o pin (1) w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . comp pin enable comp2
pic12f510/16f506 ds41268d-page 32 ? 2007 microchip technology inc. figure 5-10: block diagram of rc2 figure 5-11: block diagram of rc3 data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . comp2 0 1 vroe i/o pin (1) cv ref data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . i/o pin (1)
? 2007 microchip technology inc. ds41268d-page 33 pic12f510/16f506 figure 5-12: block diagram of rc4 figure 5-13: block diagram of rc5 data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset 0 1 c2outen c2out note 1: i/o pins have protection diodes to v dd and v ss . i/o pin (1) data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . t0cs t0cki i/o pin (1)
pic12f510/16f506 ds41268d-page 34 ? 2007 microchip technology inc. table 5-1: summary of port registers table 5-2: i/o pin function orde r of precedence (pic16f506) table 5-3: i/o pin function orde r of precedence (pic16f506) table 5-4: i/o pin function orde r of precedence (pic12f510) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a trisgpio (1) ? ? i/o control register --11 1111 --11 1111 n/a trisb (2) ? ? i/o control register --11 1111 --11 1111 n/a trisc (2) ? ? i/o control register --11 1111 --11 1111 n/a option (1) gpwu gppu t0cs tose psa ps2 ps1 ps0 1111 1111 1111 1111 n/a option (2) rbwu rbpu t0cs tose psa ps2 ps1 ps0 1111 1111 1111 1111 03h status (1) gpwuf cwuf pa0 to pd zdcc 0001 1xxx qq0q quuu (3) 03h status (2) rbwuf cwuf pa0 to pd zdcc 0001 1xxx qq0q quuu (3) 06h gpio (1) ? ? gp5 gp4 gp3 gp2 gp1 gp0 --xx xxxx --uu uuuu 06h portb (2) ? ? rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx --uu uuuu 07h portc (2) ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx --uu uuuu legend: ? = unimplemented read as ? 0 ?, x = unknown, u = unchanged, q = depends on condition. note 1: pic12f510 only. 2: pic16f506 only. 3: if reset was due to wake-up on pin change, then bit 7 = 1 . all other resets will cause bit 7 = 0 . priority rb0 rb1 rb2 rb3 rb4 rb5 1 an0/c1in+ an1/c1in- an2 input/mclr osc2/clkout osc1/clkin 2 trisb trisb c1out ?trisb trisb 3 ? ?trisb ? ? ? priority rc0 rc1 rc2 rc3 rc4 rc5 1c2in+ c2in- cv ref trisc c2out t0cki 2 trisc trisc trisc ?trisctrisc priority gp0 gp1 gp2 gp3 gp4 gp5 1 an0/c1in+ an1/c1in- an2 input/mclr osc2 osc1/clkin 2 trisio trisio c1out ? trisio trisio 3 ? ?t0cki ? ? ? 4 ? ?trisio ? ? ?
? 2007 microchip technology inc. ds41268d-page 35 pic12f510/16f506 table 5-5: requirements for digital pin operation (pic12f510) gp0 gp0 gp1 gp1 gp2 gp2 gp3 gp4 gp5 cm1con0 c1on 01 0 101 ? ? ? c1pref ? 0 ? 1 ? ? ? ? ? c1nref ? ? ? 0 ? ? ? ? ? c1t0cs ? ? ? ? ? 1 ? ? ? c1outen ? ? ? ? ? 1 ? ? ? cm2con0 c2on ? ? ? ? ? ? ? ? ? c2pref1 ? ? ? ? ? ? ? ? ? c2pref2 ? ? ? ? ? ? ? ? ? c2nref ? ? ? ? ? ? ? ? ? c2outen ? ? ? ? ? ? ? ? ? vrcon0 vroe ? ? ? ? ? ? ? ? ? vren ? ? ? ? ? ? ? ? ? option t0cs ? ? ? ? ? 0 ? ? ? adcon0 ans<1:0> 00 , 01 00 , 01 00 , 01 , 10 00 , 01 , 10 00 00 ? ? ? config mclre ? ? ? ? ? ? ? ? ? intosc ? ? ? ? ? ? ? ? ? lp ? ? ? ? ? ? ? disabled disabled extrc ? ? ? ? ? ? ? ?disabled xt ? ? ? ? ? ? ? disabled disabled note 1: multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for the pin. 2: shaded cells indicate the bit status does not affect the pins digital functionality.
pic12f510/16f506 ds41268d-page 36 ? 2007 microchip technology inc. table 5-6: requirements for digital pin operation (pic16f506 portb) (1), (2) table 5-7: requirements for digital pin operation (pic16f506 portc) (1), (2) rb0 rb0 rb0 rb1 rb1 rb2 rb2 rb3 rb4 rb5 cm1con0 c1on ? 01 0 1 01 ? ? ? c1pref ? ? 0 ? ? ? ? ? ? ? c1nref ? ? ? ? 0 ? ? ? ? ? c1t0cs ? ? ? ? ? ? ? ? ? ? c1outen ? ? ? ? ? ? 1 ? ? ? cm2con0 c2on 1 ? ? ? ? ? ? ? ? ? c2pref1 0 ? ? ? ? ? ? ? ? ? c2pref2 1 ? ? ? ? ? ? ? ? ? c2nref ? ? ? ? ? ? ? ? ? ? c2outen ? ? ? ? ? ? ? ? ? ? option t0cs ? ? ? ? ? ? ? ? ? ? adcon0 ans<1:0> 00, 01 00 , 01 00 , 01 00 , 01 , 10 00 , 01 , 10 00 00 ? ? ? config mclre ? ? ? ? ? ? ? 0 ? ? intosc ? ? ? ? ? ? ? ? ? ? lp ? ? ? ? ? ? ? ? disabled disabled extrc ? ? ? ? ? ? ? ? ? disabled xt ? ? ? ? ? ? ? ? disabled disabled ec ? ? ? ? ? ? ? ? ? disabled hs ? ? ? ? ? ? ? ? disabled disabled intosc clkout ? ? ? ? ? ? ? ? disabled disabled extrc clockout ? ? ? ? ? ? ? ? disabled disabled note 1: multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for the pin. 2: shaded cells indicate the bit status does not affect the pins digital functionality. rc0 rc0 rc1 rc1 rc2 rc3 rc4 rc4 rc5 rc5 cm2con0 c2on 0101 ? ? 01 ? ? c2pref1 ? 0 ? ? ? ? ? ? ? ? c2pref2 ? 0 ? ? ? ? ? ? ? ? c2nref ? ? ? 0 ? ? ? ? ? ? c2outen ? ? ? ? ? ? ? 1 ? ? vrcon0 vroe ? ? ? ? 0 ? ? ??? option t0cs ? ? ? ? ? ? ? ? 0 ? note 1: multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for the pin. 2: shaded cells indicate the bit status does not affect the pins digital functionality.
? 2007 microchip technology inc. ds41268d-page 37 pic12f510/16f506 5.5 i/o programming considerations 5.5.1 bidirectional i/o ports some instructions operate internally as read followed by write operations. for example, the bcf and bsf instructions read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit 5 of portb/gpio will cause all eight bits of portb/gpio to be read into the cpu, bit 5 to be set and the portb/gpio value to be written to the output latches. if another bit of portb/ gpio is used as a bidirectional i/o pin (say bit ? 0 ?) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwrit- ing the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit ? 0 ? is switched into output mode later on, the content of the data latch may now be unknown. example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., bcf , bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (?wired or?, ?wired and?). the resulting high output currents may damage the chip. example 5-1: read-modify-write instructions on an i/o port (e.g., pic16f506) 5.5.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle. whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-14). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes the file to be read into the cpu. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 5-14: successive i/o operation (pic16f506) ;initial portb settings ;portb<5:3> inputs ;portb<2:0> outputs ; ; portb latch portb pins ; ---------- ---------- bcf portb, 5 ;--01 -ppp --11 pppp bcf portb, 4 ;--10 -ppp --11 pppp movlw 007h; tris portb ;--10 -ppp --11 pppp ; note: the user may have expected the pin values to be ? --00 pppp ?. the 2nd bcf caused rb5 to be latched as the pin value (high). pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb<5:0> movwf portb nop port pin sampled here nop movf portb, w instruction executed movwf portb (write to portb) nop movf portb,w this example shows a write to portb followed by a read from portb. data setup time = (0.25 t cy ? t pd ) where: t cy = instruction cycle t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic. (read portb) port pin written here
pic12f510/16f506 ds41268d-page 38 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds41268d-page 39 pic12f510/16f506 6.0 tmr0 module and tmr0 register the timer0 module has the following features: ? 8-bit timer/counter register, tmr0 ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select: - edge select for external clock - external clock from either the t0cki pin or from the output of the comparator figure 6-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to the tmr0 register. there are two types of counter mode. the first counter mode uses the t0cki pin to increment timer0. it is selected by setting the t0cki bit (option<5>), setting the c 1t 0cs bit (cm1con0<4>) and setting the c 1 outen bit (cm1con0<6>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the t0se bit (option<4>) determines the source edge. clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.1 ?using timer0 with an external clock? . the second counter mode uses the output of the com- parator to increment timer0. it can be entered in two different ways. the first way is selected by setting the t0cs bit (option<5>), and clearing the c1t0cs bit (cm1con0<4>) (c1outen [cm1con0<6>] does not affect this mode of operation). this enables an internal connection between the comparator and the timer0. the second way is selected by setting the t0cs bit (option<5>), setting the c1t0cs bit (cm1con0) and clearing the c1outen bit (cm1con0<6>). this allows the output of the comparator onto the t0cki pin, while keeping the t0cki input active. therefore, any comparator change on the cout pin is fed back into the t0cki input. the t0se bit (option<4>) deter- mines the source edge. clearing the t0se bit selects the rising edge. restrictions on the external clock input as discussed in section 6.1 ?using timer0 with an external clock? . the prescaler may be used by either the timer0 module or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 6.2 ?prescaler? details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 6-1. figure 6-1: timer0 block diagram note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-5). 3: bit c1t0cs is located in the cm1con0 register, cm1con0<4>. 0 1 1 0 t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg ps out (2 t cy delay) ps out data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync t0se (1) t0cki pin c1t0cs (3) 1 0 internal comparator output
pic12f510/16f506 ds41268d-page 40 ? 2007 microchip technology inc. figure 6-2: timer0 timing: in ternal clock/no prescale figure 6-3: timer0 timing: internal clock/prescale 1:2 table 6-1: registers associated with timer0 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 01h tmr0 timer0 ? 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 07h cm1con0 (2) c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 1111 1111 uuuu uuuu 08h cm1con0 (3) c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 1111 1111 uuuu uuuu n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 n/a trisgpio (1) ? ? i/o control register ---- 1111 --11 1111 legend: shaded cells not used by timer0, ? = unimplemented, x = unknown, u = unchanged. note 1: the tris of the t0cki pin is overridden when t0cs = 1 . 2: for pic12f510. 3: for pic16f506. pc - 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 t0 + 2 nt0 nt0 + 1 nt0 + 2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter) pc - 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 nt0 nt0 + 1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter)
? 2007 microchip technology inc. ds41268d-page 41 pic12f510/16f506 6.1 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock require- ment is due to internal phase clock (t osc ) synchroniza- tion. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of an external clock with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-4). therefore, it is necessary for t0cki or the comparator output to be high for at least 2t osc (and a small rc delay of 2tt0h) and low for at least 2t osc (and a small rc delay of 2tt0h). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. for the external clock to meet the sampling require- ment, the ripple counter must be taken into account. therefore, it is necessary for t0cki or the comparator output to have a period of at least 4t osc (and a small rc delay of 4tt0h) divided by the prescaler value. the only requirement on t0cki or the comparator output high and low time is that they do not violate the minimum pulse width requirement of tt0h. refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 6-4 shows the delay from the external clock edge to the timer incrementing. figure 6-4: timer0 timing with external clock 6.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module or as a postscaler for the watchdog timer (wdt), respectively (see figure 10-12). for sim- plicity, this counter is being referred to as ?prescaler? throughout this data sheet. the psa and ps<2:0> bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1, x, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all ? 0 ?s. increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) prescaler output (2) (1) note 1: delay from clock input change to timer0 increment is 3t osc to 7t osc . (duration of q = t osc ). therefore, the error in measuring the interval between two edges on timer0 input = 4t osc max. 2: external clock if no prescaler selected; prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs. note: the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt and vice-versa.
pic12f510/16f506 ds41268d-page 42 ? 2007 microchip technology inc. 6.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on-the-fly? during pro- gram execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 6-1: changing prescaler (timer0 wdt) to change prescaler from the wdt to the timer0 module, use the sequence shown in example 6-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 6-2: changing prescaler (wdt timer0) figure 6-5: block diagram of the timer0/wdt prescaler clrwdt ;clear wdt clrf tmr0 ;clear tmr0 & prescaler movlw ?00xx1111?b ;these 3 lines (5, 6, 7) option ;are required only if ;desired clrwdt ;ps<2:0> are 000 or 001 movlw ?00xx1xxx?b ;set postscaler to option ;desired wdt rate clrwdt ;clear wdt and ;prescaler movlw ?xxxx0xxx? ;select tmr0, new ;prescale value and ;clock source option t cy (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1 mux m mux watchdog timer psa (1) 0 1 0 1 wdt time-out ps<2:0> (1) 8 psa (1) wdt enable bit 0 1 0 1 data bus 8 psa (1) t0cs (1) m u x m u x u x t0se (1) t0cki (2) pin note 1: t0cs, t0se, psa, ps<2:0> are bits in the option register. 2: t0cki is shared with pin gp2 on the pic12f510 and shared with rc5 on the pic16f506. 3: bit c1t0cs is located in the cm1con0 register. 1 0 comparator output c1t0cs (3)
? 2007 microchip technology inc. ds41268d-page 43 pic12f510/16f506 7.0 comparator(s) the pic12f510 contains one analog comparator module. the pic16f506 contains two comparators and a comparator voltage reference. register 7-1: cm1con0: comparator c1 control register (pic12f510) r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c1out: comparator output bit 1 = v in + > v in - 0 = v in + < v in - bit 6 c1outen : comparator output enable bit (1), (2) 1 = output of comparator is not placed on the c1out pin 0 = output of comparator is placed in the c1out pin bit 5 c1pol: comparator output polarity bit (2) 1 = output of comparator is not inverted 0 = output of comparator is inverted bit 4 c1t0cs : comparator tmr0 clock source bit (2) 1 = tmr0 clock source selected by t0cs control bit 0 = comparator output used as tmr0 clock source bit 3 c1on: comparator enable bit 1 = comparator is on 0 = comparator is off bit 2 c1nref: comparator negative reference select bit (2) 1 = c1in- pin 0 = 0.6v internal reference bit 1 c1pref: comparator positive reference select bit (2) 1 = c1in+ pin 0 = c1in- pin bit 0 c1wu : comparator wake-up on change enable bit (2) 1 = wake-up on comparator change is disabled 0 = wake-up on comparator change is enabled note 1: overrides t0cs bit for tris control of rb2. 2: when comparator is turned on, these control bits assert themselves.
pic12f510/16f506 ds41268d-page 44 ? 2007 microchip technology inc. register 7-2: cm1con0: comparator c1 control register (pic16f506) r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c1out: comparator output bit 1 = v in + > v in - 0 = v in + < v in - bit 6 c1outen : comparator output enable bit (1), (2) 1 = output of comparator is not placed on the c1out pin 0 = output of comparator is placed in the c1out pin bit 5 c1pol: comparator output polarity bit (2) 1 = output of comparator is not inverted 0 = output of comparator is inverted bit 4 c1t0cs : comparator tmr0 clock source bit (2) 1 = tmr0 clock source selected by t0cs control bit 0 = comparator output used as tmr0 clock source bit 3 c1on: comparator enable bit 1 = comparator is on 0 = comparator is off bit 2 c1nref: comparator negative reference select bit (2) 1 = c1in- pin 0 = 0.6v internal reference bit 1 c1pref: comparator positive reference select bit (2) 1 = c1in+ pin 0 = c1in- pin bit 0 c1wu : comparator wake-up on change enable bit (2) 1 = wake-up on comparator change is disabled 0 = wake-up on comparator change is enabled note 1: overrides t0cs bit for tris control of rb2. 2: when comparator is turned on, these control bits assert themselves. otherwise, the other registers have precedence.
? 2007 microchip technology inc. ds41268d-page 45 pic12f510/16f506 register 7-3: cm2con0: comparator c2 control register (pic16f506) r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c2out: comparator output bit 1 = v in + > v in - 0 = v in + < v in - bit 6 c2outen : comparator output enable bit (1), (2) 1 = output of comparator is not placed on the c2out pin 0 = output of comparator is placed in the c2out pin bit 5 c2pol: comparator output polarity bit (2) 1 = output of comparator not inverted 0 = output of comparator inverted bit 4 c2pref2: comparator positive reference select bit (2) 1 = c1in+ pin 0 = c2in- pin bit 3 c2on: comparator enable bit 1 = comparator is on 0 = comparator is off bit 2 c2nref: comparator negative reference select bit (2) 1 = c2in- pin 0 = cv ref bit 1 c2pref1: comparator positive reference select bit (2) 1 = c2in+ pin 0 = c2pref2 controls analog input selection bit 0 c2wu : comparator wake-up on change enable bit (2) 1 = wake-up on comparator change is disabled 0 = wake-up on comparator change is enabled. note 1: overrides tocs bit for tris control of rc4. 2: when comparator is turned on, these control bits assert themselves. otherwise, the other registers have precedence.
pic12f510/16f506 ds41268d-page 46 ? 2007 microchip technology inc. figure 7-1: comparator 1 blo ck diagram for pic12f510/16f506 figure 7-2: comparator 2 blo ck diagram (pic16f506 only) note 1: when c1on = 0 , the comparator, c1, will produce a ? 0 ? output to the xor gate. mux c1 c1pol c1out 0 1 c1on (1) c1pref 1 0 c1 outen 0.6v c1out c1in- c1in+ c1in- dq en cl nreset c1nref mux + - c1wu c1wuf to data bus rd_cm1con0 q3 * rd_cm1con0 (internal reference) mux c2pol c2out 1 0 c2pref1 c2nref note 1: when c2on = 0 , the comparator, c2, will produce a ? 0 ? output to the xor gate. cv ref dq en cl rd_cm2con0 to nreset data bus c2 c2on (1) c2in+ mux 1 0 c2pref2 c1in+ c2in- + - mux 1 0 c2in- c2out c2outen c2wu c2wuf q3 * rd_cm2con0
? 2007 microchip technology inc. ds41268d-page 47 pic12f510/16f506 7.1 comparator operation a single comparator is shown in figure 7-3 along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. the shaded area of the output of the comparator in figure 7-3 represent the uncertainty due to input offsets and response time. see table 13-1 for common mode voltage. figure 7-3: single comparator 7.2 comparator reference an internal reference signal may be used depending on the comparator operating mode. the analog signal that is present at v in - is compared to the signal at v in +, and the digital output of the comparator is adjusted accord- ingly (figure 7-3). please see section 8.0 ?compara- tor voltage reference module (pic16f506 only)? for internal reference specifications. 7.3 comparator response time response time is the minimum time after selecting a new reference voltage or input source before the com- parator output is to have a valid level. if the comparator inputs are changed, a delay must be used to allow the comparator to settle to its new state. please see table 13-1 for comparator response time specifications. 7.4 comparator output the comparator output is read through the cm1con0 or cm2con0 register. this bit is read-only. the comparator output may also be used externally, see figure 7-3. 7.5 comparator wake-up flag the comparator wake-up flag is set whenever all of the following conditions are met: ?c1wu = 0 (cm1con0<0>) or c2wu = 0 (cm2con0<0>) ? cm1con0 or cm2con0 has been read to latch the last known state of the c1out and c2out bit ( movf cm1con0 , w ) ? device is in sleep ? the output of a comparator has changed state the wake-up flag may be cleared in software or by another device reset. 7.6 comparator operation during sleep when the comparator is enabled it is active. to mini- mize power consumption while in sleep mode, turn off the comparator before entering sleep. 7.7 effects of reset a power-on reset (por) forces the cm2con0 register to its reset state. this forces the comparator input pins to analog reset mode. device current is minimized when analog inputs are present at reset time. 7.8 analog input connection considerations a simplified circuit for an analog input is shown in figure 7-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up may occur. a maximum source impedance of 10 k is recom- mended for the analog sources. any external compo- nent connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. ? + v in + v in - result result v in - v in + note: analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified.
pic12f510/16f506 ds41268d-page 48 ? 2007 microchip technology inc. figure 7-4: analog input mode table 7-1: registers associated with comparator module add name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 03h status gpwuf cwuf pa0 to pd zdcc 0001 1xxx qq0q quuu 07h cm1con0 (1) c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 1111 1111 uuuu uuuu 08h cm1con0 (2) c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 1111 1111 uuuu uuuu 0bh cm2con0 (2) c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu 1111 1111 uuuu uuuu n/a trisb (2) ? ? i/o control register --11 1111 --11 1111 n/a trisc (2) ? ? i/o control register --11 1111 --11 1111 n/a trisgpio (1) ? ? i/o control register --11 1111 --11 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?, q = depends on condition. note 1: pic12f510 only. 2: pic16f506 only. va r s < 10 k a in c pin 5pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin r ic = interconnect resistance r s = source impedance va = analog voltage
? 2007 microchip technology inc. ds41268d-page 49 pic12f510/16f506 8.0 comparator voltage reference module (pic16f506 only) the comparator voltage reference module also allows the selection of an internally generated voltage refer- ence for one of the c2 comparator inputs. the vrcon register (register 8-1) controls the voltage reference module shown in figure 8-1. 8.1 configuring the voltage reference the voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range. equation 8-1 determines the output voltages: equation 8-1: 8.2 voltage reference accuracy/error the full range of v ss to v dd cannot be realized due to construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 8-1) keep cv ref from approaching v ss or v dd . the excep- tion is when the module is disabled by clearing the vren bit (vrcon<7>). when disabled, the reference voltage is v ss when vr<3:0> is ? 0000 ? and the vrr (vrcon<5>) bit is set. this allows the comparator to detect a zero-crossing and not consume the cv ref module current. the voltage reference is v dd derived and, therefore, the cv ref output changes with fluctuations in v dd . the tested absolute accuracy of the comparator voltage reference can be found in section 13.2 ?dc charac- teristics: pic12f510/16f506 (extended)? . vrr = 1 (low range): cv ref = (vr<3:0>/24) x v dd vrr = 0 (high range): cv ref = (v dd /4) + (vr<3:0> x v dd /32) register 8-1: vrcon: voltage reference control register (pic16f506 only) r/w-0 r/w-0 r/w-1 u-1 r/w-1 r/w-1 r/w-1 r/w-1 vren vroe vrr ?vr3vr2vr1vr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0?, except if denoted otherwise -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 vren: cv ref enable bit 1 = cv ref is powered on 0 = cv ref is powered down, no current is drawn bit 6 vroe: cv ref output enable bit (1) 1 = cv ref output is enabled 0 = cv ref output is disabled bit 5 vrr: cv ref range selection bit 1 = low range 0 = high range bit 4 unimplemented: read as ? 1 ? bit 3-0 vr<3:0> cv ref value selection bit when v rr = 1 : cv ref = (vr<3:0>/24)*v dd when v rr = 0 : cv ref = v dd /4+(vr<3:0>/32)*v dd note 1: when this bit is set, the tris for the cv ref pin is overridden and the analog voltage is placed on the cv ref pin. 2: cv ref controls for ratio metric reference applies to comparator 2 on the pic16f506 only.
pic12f510/16f506 ds41268d-page 50 ? 2007 microchip technology inc. figure 8-1: comparator volt age reference block diagram table 8-1: registers associated with comparator voltage reference add name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 0ch vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 001- 1111 001- 1111 08h cm1con0 (1) c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 1111 1111 uuuu uuuu 0bh cm2con0 (1) c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu 1111 1111 uuuu uuuu legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. note 1: pic16f506 only. v dd 8r r r vren 16-1 analog mux cv ref to comparator 2 input vr<3:0> v ren vr<3:0> = 0000 vrr vrr 8r rr 16 stages rc2/cv ref v roe
? 2007 microchip technology inc. ds41268d-page 51 pic12f510/16f506 9.0 analog-to-digital (a/d) converter the a/d converter allows conversion of an analog signal into an 8-bit digital signal. 9.1 clock divisors the adc has 4 clock source settings adcs<1:0>. there are 3 divisor values 16, 8 and 4. the fourth set- ting is intosc with a divisor of 4. these settings will allow a proper conversion when using an external oscillator at speeds from 20 mhz to 350 khz. using an external oscillator at a frequency below 350 khz (tad > 50 s) requires the adc oscillator setting to be intosc/4 for valid adc results. the adc requires 13 t ad periods to complete a conversion. the divisor values do not affect the number of t ad periods required to perform a conversion. the divisor values determine the length of the t ad period. when the adcs<1:0> bits are changed while an adc conversion is in process, the new adc clock source will not be selected until the next conversion is started. this clock source selection will be lost when the device enters sleep. 9.1.1 voltage reference there is no external voltage reference for the adc. the adc reference voltage will always be v dd . 9.1.2 analog mode selection the ans<1:0> bits are used to configure pins for analog input. upon any reset, ans<1:0> defaults to 11. this configures pins an0, an1 and an2 as analog inputs. pins configured as analog inputs are not avail- able for digital output. users should not change the ans bits while a conversion is in process. ans bits are active regardless of the condition of adon. 9.1.3 adc channel selection the chs bits are used to select the analog channel to be sampled by the adc. the chs<1:0> bits can be changed at any time without adversely effecting a con- version. to acquire an analog signal the chs<1:0> selection must match one of the pin(s) selected by the ans<1:0> bits. when the adc is on (adon = 1 ) and a channel is selected that is also being used by the comparator, then both the comparator and the adc will see the analog voltage on the pin. when the chs<1:0> bits are changed during an adc conversion, the new channel will not be selected until the current conversion is completed. this allows the current conversion to complete with valid results. all channel selection information will be lost when the device enters sleep. table 9-1: channel select (adcs) bits after an event 9.1.4 the go/done bit the go/done bit is used to determine the status of a conversion, to start a conversion and to manually halt a conversion in process. setting the go/done bit starts a conversion. when the conversion is complete, the adc module clears the go/done bit. a conversion can be terminated by manually clearing the go/done bit while a conversion is in process. manual termination of a conversion may result in a partially converted result in adres. the go/done bit is cleared when the device enters sleep, stopping the current conversion. the adc does not have a dedicated oscillator, it runs off of the instruc- tion clock. therefore, no conversion can occur in sleep. the go/done bit cannot be set when adon is clear. note: it is the users responsibility to ensure that use of the adc and comparator simulta- neously on the same pin, does not adversely affect the signal being monitored or adversely effect device operation. event adcs<1:0> mclr 11 conversion completed cs<1:0> conversion terminated cs<1:0> power-on 11 wake from sleep 11
pic12f510/16f506 ds41268d-page 52 ? 2007 microchip technology inc. 9.1.5 sleep this adc does not have a dedicated adc clock, and therefore, no conversion in sleep is possible. if a conversion is underway and a sleep command is executed, the go/done and adon bit will be cleared. this will stop any conversion in process and power- down the adc module to conserve power. due to the nature of the conversion process, the adres may con- tain a partial conversion. at least 1 bit must have been converted prior to sleep to have partial conversion data in adres. the adcs and chs bits are reset to their default condition; ans<1:0> = 11 and chs<1:0> = 11 . ? for accurate conversions, t ad must meet the following: ?500ns < t ad < 50 s ?t ad = 1 /(f osc /divisor) shaded areas indicate t ad out of range for accurate conversions. if analog input is desired at these frequencies, use intosc/4 for the adc clock source. table 9-2: t ad for adcs settings with various oscillators note 1: when operating with external oscillator frequencies of 16 mhz or higher, better adc performance will result from selection of a suitable f osc divisor value from table 9-2 than from use of the intosc/4 option for the adc clock. table 9-3: effects of sleep on adcon0 source adcs <1:0> divisor 20 (1) mhz 16 (1) mhz 8mhz 4mhz 1mhz 500 khz 350 khz 200 khz 100 khz 32 khz intosc 11 4 ? ?.5 s1 s ? ? ? ? ? ? fosc 10 4 .2 s .25 s.5 s1 s4 s8 s11 s20 s40 s 125 s fosc 01 8 .4 s.5 s1 s2 s8 s16 s23 s40 s 80 s 250 s fosc 00 16 .8 s1 s2 s4 s16 s32 s46 s 80 s 160 s 500 s ans1 ans0 adcs1 adcs0 chs1 chs0 go/done adon entering sleep unchanged unchanged 111100 wake or reset 11111100
? 2007 microchip technology inc. ds41268d-page 53 pic12f510/16f506 9.1.6 analog conversion result register the adres register contains the results of the last conversion. these results are present during the sam- pling period of the next analog conversion process. after the sampling period is over, adres is cleared (= 0 ). a ?leading one? is then right shifted into the adres to serve as an internal conversion complete bit. as each bit weight, starting with the msb, is con- verted, the leading one is shifted right and the con- verted bit is stuffed into adres. after a total of 9 right shifts of the ?leading one? have taken place, the conver- sion is complete; the ?leading one? has been shifted out and the go/done bit is cleared. if the go/done bit is cleared in software during a con- version, the conversion stops. the data in adres is the partial conversion result. this data is valid for the bit weights that have been converted. the position of the ?leading one? determines the number of bits that have been converted. the bits that were not converted before the go/done was cleared are unrecoverable. register 9-1: adcon0: a/d cont rol register (pic12f510) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ans1 ans0 adcs1 adcs0 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 ans<1:0>: adc analog input pin select bits (1), (2) 00 = no pins configured for analog input 01 = an2 configured as an analog input 10 = an2 and an0 configured as analog inputs 11 = an2, an1 and an0 configured as analog inputs bit 5-4 adcs<1:0>: adc conversion clock select bits 00 = f osc /16 01 = f osc /8 10 = f osc /4 11 = intosc/4 bit 3-2 chs<1:0>: adc channel select bits 00 = channel an0 01 = channel an1 10 = channel an2 11 = 0.6v absolute voltage reference bit 1 go/done : adc conversion status bit (4) 1 = adc conversion in progress. setting this bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc is done converting. 0 = adc conversion completed/not in progress. manually clearing this bit while a conversion is in process terminates the current conversion. bit 0 adon: adc enable bit 1 = adc module is operating 0 = adc module is shut-off and consumes no power note 1: when the ans bits are set, the channels selected will automatically be forced into analog mode, regard- less of the pin function previously defined. the only exception to this is the comparator, where the analog input to the comparator and the adc will be active at the same time. it is the users responsibility to ensure that the adc loading on the comparator input does not affect their application. 2: the ans<1:0> bits are active regardless of the condition of adon. 3: chs<1:0> bits default to 11 after any reset. 4: if the adon bit is clear, the go/done bit cannot be set.
pic12f510/16f506 ds41268d-page 54 ? 2007 microchip technology inc. example 9-1: performing an analog-to-digital conversion example 9-2: channel selection change during conversion register 9-2: adres register r-x r-x r-x r-x r-x r-x r-x r-x adres7 adres6 adres5 adres4 adres3 adres2 adres1 adres0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ;sample code operates out of bank0 movlw 0xf1 ;configure a/d movwf adcon0 bsf adcon0, 1 ;start conversion loop0 btfsc adcon0, 1;wait for ?done? goto loop0 movf adres, w ;read result movwf result0 ;save result bsf adcon0, 2 ;setup for read of ;channel 1 bsf adcon0, 1 ;start conversion loop1 btfsc adcon0, 1;wait for ?done? goto loop1 movf adres, w ;read result movwf result1 ;save result bsf adcon0, 3 ;setup for read of bcf adcon0, 2 ;channel 2 bsf adcon0, 1 ;start conversion loop2 btfsc adcon0, 1;wait for ?done? goto loop2 movf adres, w ;read result movwf result2 ;save result movlw 0xf1 ;configure a/d movwf adcon0 bsf adcon0, 1 ;start conversion bsf adcon0, 2 ;setup for read of ;channel 1 loop0 btfsc adcon0, 1;wait for ?done? goto loop0 movf adres, w ;read result movwf result0 ;save result bsf adcon0, 1 ;start conversion bsf adcon0, 3 ;setup for read of bcf adcon0, 2 ;channel 2 loop1 btfsc adcon0, 1;wait for ?done? goto loop1 movf adres, w ;read result movwf result1 ;save result bsf adcon0, 1 ;start conversion loop2 btfsc adcon0, 1;wait for ?done? goto loop2 movf adres, w ;read result movwf result2 ;save result clrf adcon0 ;optional: returns ;pins to digital mode and turns off ;the adc module
? 2007 microchip technology inc. ds41268d-page 55 pic12f510/16f506 10.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits that deal with the needs of real- time applications. the pic12f510/16f506 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power- saving operating modes and offer code protection. these features are: ? oscillator selection ? reset: - power-on reset (por) - device reset timer (drt) - wake-up from sleep on pin change ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming? (icsp?) ?clock out the pic12f510/16f506 devices have a watchdog timer, which can be shut off only through configuration bit wdte. it runs off of its own rc oscillator for added reliability. if using hs (pic16f506), xt or lp selectable oscillator options, there is always a delay, provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. if using intosc, extrc or ec there is an 1.125 ms (nominal) delay only on v dd power-up. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low-current power-down mode. the user can wake-up from sleep through a change-on-input pin or through a watchdog timer time-out. several oscillator options are also made available to allow the part to fit the application, including an internal 4/8 mhz oscillator. the extrc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. 10.1 configuration bits the pic12f510/16f506 configuration words consist of 12 bits. configuration bits can be programmed to select various device configurations. three bits are for the selection of the oscillator type; (two bits on the pic12f510), one bit is the watchdog timer enable bit, one bit is the mclr enable bit and one bit is for code protection (register 10-1, register 10-2).
pic12f510/16f506 ds41268d-page 56 ? 2007 microchip technology inc. register 10-1: config : configuration word register (pic12f510) (1) ? ? ? ? ? ? ? ? bit 15 bit 8 ? ? ioscfs mclre cp wdte fosc1 fosc0 bit 7 bit 0 bit 15-6 unimplemented : read as ? 1 ? bit 5 ioscfs: internal oscillator frequency select bit 1 = 8 mhz intosc speed 0 = 4 mhz intosc speed bit 4 mclre: master clear enable bit 1 = gp3/mclr pin functions as mclr 0 = gp3/mclr pin functions as gp3, mclr internally tied to v dd bit 3 cp : code protection bit 1 = code protection off 0 = code protection on bit 2 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 fosc<1:0>: oscillator selection bits 00 = lp oscillator with 18 ms drt 01 = xt oscillator with 18 ms drt 10 = intosc with 1.125 ms drt (2) 11 = extrc with 1.125 ms drt (2) note 1: refer to the ? pic12f510 memory programming specification ? (ds41257) to determine how to access the configuration word. 2: it is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal) drt will result in acceptable operation. refer to electrical specifications for v dd rise time and stability require- ments for this mode of operation.
? 2007 microchip technology inc. ds41268d-page 57 pic12f510/16f506 register 10-2: config : configuration word register (pic16f506) (1) ? ? ? ? ? ? ? ? bit 15 bit 8 ? ioscfs mclre cp wdte fosc2 fosc1 fosc0 bit 7 bit 0 bit 11-7 unimplemented : read as ? 1 ? bit 6 ioscfs: internal oscillator frequency select bit 1 = 8 mhz intosc speed 0 = 4 mhz intosc speed bit 5 mclre: master clear enable bit 1 = rb3/mclr pin functions as mclr 0 = rb3/mclr pin functions as rb3, mclr tied internally to v dd bit 4 cp : code protection bit 1 = code protection off 0 = code protection on bit 3 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0 fosc<2:0>: oscillator selection bits 000 = lp oscillator and 18 ms drt 001 = xt oscillator and 18 ms drt 010 = hs oscillator and 18 ms drt 011 = ec oscillator with rb4 function on rb4/osc2/clkout and 1.125 ms drt (2) 100 = intosc with rb4 function on rb4/osc2/clkout and 1.125 ms drt (2) 101 = intosc with clkout function on rb4/osc2/clkout and 1.125 ms drt (2) 110 = extrc with rb4 function on rb4/osc2/clkout and 1.125 ms drt (2) 111 = extrc with clkout function on rb4/osc2/clkout and 1.125 ms drt (2) note 1: refer to the ? pic16f506 memory programming specification ? (ds41258) to determine how to access the configuration word. 2: it is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal) drt will result in acceptable operation. refer to electrical specifications for v dd rise time and stability require- ments for this mode of operation.
pic12f510/16f506 ds41268d-page 58 ? 2007 microchip technology inc. 10.2 oscillator configurations 10.2.1 oscillator types the pic12f510/16f506 devices can be operated in up to six different oscillator modes. the user can program up to three configuration bits (fosc<1:0> [pic12f510], fosc<2:0> [pic16f506]). to select one of these modes: ?lp: low-power crystal ?xt: crystal/resonator ?hs: high-speed crystal/resonator (pic16f506 only) ?intosc: internal 4/8 mhz oscillator ?extrc: external resistor/capacitor ?ec: external high-speed clock input (pic16f506 only) 10.2.2 crystal oscillator/ceramic resonators in hs (pic16f506), xt or lp modes, a crystal or ceramic resonator is connected to the (gp5/rb5)/ osc1/(clkin) and (gp4/rb4)/osc2/(clkout) pins to establish oscillation (figure 10-1). the pic12f510/ 16f506 oscillator designs require the use of a parallel cut crystal. use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. when in hs (pic16f506), xt or lp modes, the device can have an external clock source drive the (gp5/ rb5)/osc1/clkin pin (figure 10-2). when the part is used in this fashion, the output drive levels on the osc2 pin are very weak. this pin should be left open and unloaded. also, when using this mode, the external clock should observe the frequency limits for the clock mode chosen (hs, xt or lp). figure 10-1: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 10-2: exter nal clock input operation (hs, xt or lp osc configuration) table 10-1: capacitor selection for ceramic resonators ? pic12f510/16f506 (1) note 1: this device has been designed to per- form to the parameters of its data sheet. it has been tested to an electrical specification designed to determine its conformance with these parameters. due to process differences in the manufacture of this device, this device may have different performance charac- teristics than its earlier version. these differences may cause this device to perform differently in your application than the earlier version of this device. 2: the user should verify that the device oscillator starts and performs as expected. adjusting the loading capacitor values and/or the oscillator mode may be required. osc. type resonator freq. cap. range c1 cap. range c2 xt 4.0 mhz 30 pf 30 pf hs (2) 16 mhz 10-47 pf 10-47 pf note 1: these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. 2: pic16f506 only. note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf approx. value = 10 m . c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic12f510 pic16f506 clock from ext. system osc1 osc2 open pic12f510 pic16f506
? 2007 microchip technology inc. ds41268d-page 59 pic12f510/16f506 table 10-2: capacitor selection for crystal oscillator ? pic12f510/16f506 (2) 10.2.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crystal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good perfor- mance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance or one with series resonance. figure 10-3 shows implementation of a parallel reso- nant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k resistor provides the negative feedback for stability. the 10 k potenti- ometers bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 10-3: external parallel resonant crystal oscillator circuit figure 10-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator circuit. the 330 resistors provide the negative feedback to bias the inverters in their linear region. figure 10-4: external series resonant crystal oscillator circuit 10.2.4 external rc oscillator for timing insensitive applications, the extrc device option offers additional cost savings. the extrc oscil- lator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit-to-unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 10-5 shows how the r/c combination is connected to the pic12f510/16f506 devices. for r ext values below 5.0 k , the oscillator operation may become unstable or stop completely. for very high r ext values (e.g., 1 m ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping r ext between 5.0 k and 100 k . osc. type resonator freq. cap.range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 200 khz 1 mhz 4 mhz 47-68 pf 15 pf 15 pf 47-68 pf 15 pf 15 pf hs (3) 20 mhz 15-47 pf 15-47 pf note 1: for v dd > 4.5v, c1 = c2 30 pf is recommended. 2: these values are for design guidance only. rs may be required to avoid over- driving crystals beyond the drive level specification. since each crystal has its own characteristics, the user should con- sult the crystal manufacturer for appropri- ate values of external components. 3: pic16f506 only. 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 clkin to o t h e r devices pic12f510 pic16f506 330 74as04 74as04 clkin to other devices xtal 330 74as04 0.1 mf pic12f510 pic16f506
pic12f510/16f506 ds41268d-page 60 ? 2007 microchip technology inc. although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no capacitance or small external capacitance, the oscilla- tion frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. section 13.0 ?electrical characteristics? , shows rc frequency variation from part-to-part due to normal process variation. the variation is larger for larger val- ues of r (since leakage current variation will affect rc frequency more for large r) and for smaller values of c (since variation of input capacitance will affect rc frequency more). also, see the electrical specifications section for variation of oscillator frequency due to v dd for given r ext /c ext values, as well as frequency variation due to operating temperature for given r, c and v dd values. figure 10-5: external rc oscillator mode 10.2.5 internal 4/8 mhz rc oscillator the internal rc oscillator provides a fixed 4/8 mhz (nominal) system clock (see section 13.0 ?electrical characteristics? for information on variation over voltage and temperature). in addition, a calibration instruction is programmed into the last address of memory, which contains the calibra- tion value for the internal rc oscillator. this location is always uncode protected, regardless of the code-pro- tect settings. this value is programmed as a movlw xx instruction where xx is the calibration value, and is placed at the reset vector. this will load the w register with the calibration value upon reset and the pc will then roll over to the users program at address 0x000. the user then has the option of writing the value to the osccal register (05h) or ignoring it. osccal, when written to with the calibration value, will ?trim? the internal oscillator to remove process variation from the oscillator frequency. for the pic12f510/16f506 devices, only bits <7:1> of osccal are used for calibration. see register 4-5 for more information. v dd r ext c ext v ss osc1 internal clock n f osc /4 osc2/clkout pic12f510 pic16f506 note: erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. note: the 0 bit of osccal is unimplemented and should be written as ? 0 ? when modify- ing osccal for compatibility with future devices.
? 2007 microchip technology inc. ds41268d-page 61 pic12f510/16f506 10.3 reset the device differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt time-out reset during normal operation ? wdt time-out reset during sleep ? wake-up from sleep reset on pin change ? wake-up from sleep reset on comparator change some registers are not reset in any way, they are unknown on por and unchanged in any other reset. most other registers are reset to ?reset state? on power-on reset (por), mclr , wdt or wake-up from sleep reset on pin change or wake-up from sleep reset on comparator change. the exceptions are to , pd , cwuf and rbwuf/gpwuf bits. they are set or cleared differently in different reset situations. these bits are used in software to determine the nature of reset. see table 10-4 for a full description of reset states of all registers. table 10-3: reset conditions for registers ? pic12f510 register address power-on reset mclr reset, wdt time-out, wake-up on pin change, wake-up on comparator change w? qqqq qqqu (1) qqqq qqqu (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pcl 02h 1111 1111 1111 1111 status 03h 0001 1xxx qq0q quuu (2) fsr 04h 110x xxxx 11uu uuuu osccal 05h 1111 111- uuuu uuu- gpio 06h --xx xxxx --uu uuuu cm1con0 07h 1111 1111 uuuu uuuu adcon0 08h 1111 1100 uu11 1100 adres 09h xxxx xxxx uuuu uuuu option ? 1111 1111 1111 1111 trisio ? --11 1111 --11 1111 legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?, q = value depends on condition. note 1: bits <7:2> of w register contain oscillator calibration values due to movlw xx instruction at top of memory. 2: see table 10-5 for reset value for specific conditions.
pic12f510/16f506 ds41268d-page 62 ? 2007 microchip technology inc. table 10-4: reset conditions for registers ? pic16f506 table 10-5: reset condition for special registers register address power-on reset mclr reset, wdt time-out, wake-up on pin change, wake-up on comparator change w? qqqq qqqu (1) qqqq qqqu (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pcl 02h 1111 1111 1111 1111 status 03h 0001 1xxx 10uq quuu (2) fsr 04h 100x xxxx 10uu uuuu osccal 05h 1111 111- uuuu uuu- portb 06h --xx xxxx --uu uuuu portc 07h --xx xxxx --uu uuuu cm1con0 08h 1111 1111 uuuu uuuu adcon0 09h 1111 1100 uu11 1100 adres 0ah xxxx xxxx uuuu uuuu cm2con0 0bh 1111 1111 uuuu uuuu vrcon 0ch 0011 1111 uuuu uuuu option ? 1111 1111 1111 1111 trisb ? --11 1111 --11 1111 trisc ? --11 1111 --11 1111 legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?, q = value depends on condition. note 1: bits <7:2> of w register contain oscillator calibration values due to movlw xx instruction at top of memory. 2: see table 10-5 for reset value for specific conditions. status addr: 03h pcl addr: 02h power-on reset 0001 1xxx 1111 1111 mclr reset during normal operation 000u uuuu 1111 1111 mclr reset during sleep 0001 0uuu 1111 1111 wdt reset during sleep 0000 0uuu 1111 1111 wdt reset normal operation 0000 uuuu 1111 1111 wake-up from sleep reset on pin change 1001 0uuu 1111 1111 wake from sleep reset on comparator change 0101 0uuu 1111 1111 legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?.
? 2007 microchip technology inc. ds41268d-page 63 pic12f510/16f506 10.3.1 mclr enable this configuration bit, when unprogrammed (left in the ? 1 ? state), enables the external mclr function. when programmed, the mclr function is tied to the internal v dd and the pin is assigned to be a i/o. see figure 10-6. figure 10-6: mclr select 10.4 power-on reset (por) the pic12f510/16f506 devices incorporate an on- chip power-on reset (por) circuitry, which provides an internal chip reset for most power-up situations. the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper oper- ation. the por is active regardless of the state of the mclr enable bit. an internal weak pull-up resistor is implemented using a transistor (refer to table 13-3 for the pull-up resistor ranges). this will eliminate external rc components usually needed to create an external power-on reset. a maximum rise time for v dd is spec- ified. see section 13.0 ?electrical characteristics? for details. when the devices start normal operation (exit the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the devices must be held in reset until the operating parameters are met. a simplified block diagram of the on-chip power-on reset circuit is shown in figure 10-7. the power-on reset circuit and the device reset timer (see section 10.5 ?device reset timer (drt)? ) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr , internal or external, to be high. after the time-out period, it will reset the reset latch and thus end the on-chip reset signal. a power-up example where mclr is held low is shown in figure 10-8. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 10-9, the on-chip power-on reset feature is being used (mclr and v dd are tied together or the pin is programmed to be (gp3/rb3). the v dd is stable before the start-up timer times out and there is no prob- lem in getting a proper reset. however, figure 10-10 depicts a problem situation where v dd rises too slowly. the time between when the drt senses that mclr is high and when mclr and v dd actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip may not function correctly. for such situations, we recommend that external rc circuits be used to achieve longer por delay times (figure 10-9). for additional information, refer to application notes an522, ?power-up considerations? (ds00522) and an607, ?power-up trouble shooting? (ds00607). (gp3/rb3)/mclr /v pp mclre internal mclr gpwu /rbwu note: when the devices start normal operation (exit the reset condition), device operat- ing parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met.
pic12f510/16f506 ds41268d-page 64 ? 2007 microchip technology inc. figure 10-7: simplified block di agram of on-chip reset circuit figure 10-8: time-out sequ ence on power-up (mclr pulled low) figure 10-9: time-out sequ ence on power-up (mclr tied to v dd ): fast v dd rise time sq r q v dd (gp3/rb3)/mclr /v pp power-up detect por (power-on reset) wdt reset chip reset mclre wake-up on pin change reset start-up timer (10 ms, 1.125 ms wdt time-out pin change sleep mclr reset or 18 ms) comparator change wake-up on comparator change v dd mclr internal por drt time-out internal reset tdrt v dd mclr internal por drt time-out internal reset tdrt
? 2007 microchip technology inc. ds41268d-page 65 pic12f510/16f506 figure 10-10: time-out sequ ence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset tdrt v1 note: when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 v dd min.
pic12f510/16f506 ds41268d-page 66 ? 2007 microchip technology inc. 10.5 device reset timer (drt) on the pic12f510/16f506 devices, the drt runs any time the device is powered up. drt runs from reset and varies based on oscillator selection and reset type (see table 10-6). the drt operates from a free running on-chip oscilla- tor that is separate from intosc. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd minimum and for the oscillator to stabilize. oscillator circuits, based on crystals or ceramic resona- tors, require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the devices in a reset for a set period, as stated in table 10-6, after mclr has reached a logic high (v ih mclr ) level. programming (gp3/rb3)/mclr /v pp as mclr and using an external rc network connected to the mclr input is not required in most cases. this allows savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the (gp3/rb3)/mclr / v pp pin as a general purpose input. the drt delays will vary from chip-to-chip due to v dd , temperature and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out from sleep. this is particularly important for applications using the wdt to wake from sleep mode automatically. reset sources are por, mclr , wdt time-out, wake- up on pin change and wake-up on comparator change. see section 10.9.2 ?wake-up from sleep reset?, notes 1, 2 and 3 . 10.6 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator that does not require any external components. this rc oscillator is separate from the external rc oscillator of the (gp5/rb5)/osc1/clkin pin and the internal 4/8 mhz oscillator. this means that the wdt will run even if the main processor clock has been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset generates a device reset. the to bit (status<4>) will be cleared upon a watchdog timer reset. the wdt can be permanently disabled by program- ming the configuration wdte as a ? 0 ? (see section 10.1 ?configuration bits? ). refer to the pic12f510/16f506 programming specifications to determine how to access the configuration word. table 10-6: typical drt periods 10.6.1 wdt period the wdt has a nominal time-out period of 18 ms (with no prescaler). if a longer time-out period is desired, a prescaler with a divisor ratio of up to 1:128 can be assigned to the wdt (under software control) by writing to the option register. thus, a time-out period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to-part process variations (see dc specs). under worst-case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 10.6.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. oscillator configuration por reset subsequent resets lp 18 ms 18 ms xt 18 ms 18 ms hs (1) 18 ms 18 ms ec (1) 1.125 ms 10 s intosc 1.125 ms 10 s extrc 1.125 ms 10 s note 1: pic16f506 only note: it is the responsibility of the application designer to ensure the use of the 1.125 ms nominal drt will result in acceptable operation. refer to electrical specifications for v dd rise time and stability requirements for this mode of operation.
? 2007 microchip technology inc. ds41268d-page 67 pic12f510/16f506 figure 10-11: watchdo g timer block diagram table 10-7: summary of registers as sociated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a option (1) gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 n/a option (2) rbwu rbpu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: shaded boxes = not used by watchdog timer. ? = unimplemented, read as ? 0 ?, u = unchanged. note 1: pic12f510 only. 2: pic16f506 only. (figure 6-5) postscaler note 1: t0cs, t0se, psa, ps<2:0> are bits in the option register. wdt time-out watchdog timer from timer0 clock source wdte psa postscaler 8-to-1 mux ps<2:0> (figure 6-4) to timer0 0 1 m u x 1 0 psa mux
pic12f510/16f506 ds41268d-page 68 ? 2007 microchip technology inc. 10.7 time-out sequence, power-down and wake-up from sleep status bits (to , pd , gpwuf/rbwuf) the to , pd and (gpwuf/rbwuf) bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr or watchdog timer (wdt) reset. table 10-8: to /pd /(gpwuf/rbwuf) status after reset 10.8 reset on brown-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic12f510/16f506 devices when a brown- out occurs, external brown-out protection circuits may be built, as shown in figure 10-12 and figure 10-13. figure 10-12: brown-out protection circuit 1 figure 10-13: brown-out protection circuit 2 figure 10-14: brown-out protection circuit 3 cwuf gpwuf/ rbwuf to pd reset caused by 0000wdt wake-up from sleep 0 0 0 u wdt time-out (not from sleep) 0010mclr wake-up from sleep 0 0 1 1 power-up 00uumclr not during sleep 0 1 1 0 wake-up from sleep on pin change 1 0 1 0 wake-up from sleep on comparator change legend: u = unchanged note 1: this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). 2: pin must be configured as mclr . 33k 10k 40k (1) v dd mclr (2) pic12f510 v dd q1 pic16f506 note 1: this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: pin must be configured as mclr . v dd ? r1 r1 + r2 = 0.7v r2 40k (1) v dd mclr (2) pic12f510 r1 q1 v dd pic16f506 note: this brown-out protection circuit employs microchip technology?s mcp809 microcon- troller supervisor. there are 7 different trip point selections to accommodate 5v to 3v systems. mclr pic12f510 v dd v dd v ss rst mcp809 v dd bypass capacitor pic16f506
? 2007 microchip technology inc. ds41268d-page 69 pic12f510/16f506 10.9 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep reset). 10.9.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driving low or high-impedance). for lowest current consumption while powered down, all input pins should be at v dd or v ss and (gp3/rb3)/ mclr /v pp pin must be at a logic high level if mclr is enabled. 10.9.2 wake-up from sleep reset the device can wake-up from sleep through one of the following events: 1. an external reset input on (gp3/rb3)/mclr / v pp pin when configured as mclr . 2. a watchdog timer time-out reset (if wdt was enabled). 3. a change-on-input pin gp0/rb0, gp1/rb1, gp3/rb3 or rb4 when wake-up on change is enabled. 4. a change in the comparator ouput bits, c1out and c2out (if comparator wake-up is enabled). these events cause a device reset. the to , pd , cwuf and gpwuf/rbwuf bits can be used to deter- mine the cause of device reset. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the cwuf bit indicates a change in comparator output state while the device was in sleep. the gpwuf/rbwuf bit indicates a change in state while in sleep at pins gp0/rb0, gp1/rb1, gp3/rb3 or rb4 (since the last file or bit operation on gp/rb port). the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. 10.10 program verification/code protection if the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. the first 64 locations and the last location (osccal) can be read, regardless of the code protection bit setting. the last memory location can be read regardless of the code protection bit setting on the pic12f510/16f506 devices. 10.11 id locations four memory locations are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always set the upper 4 bits as ? 1 ?s. the upper 4 bits are unimplemented. these locations can be read regardless of the code protect setting. note: a device reset generated by a wdt time-will not drive the mclr pin low. note: caution: right before entering sleep, read the input pins. when in sleep, wake- up occurs when the values at the pins change from the state they were in at the last reading. if a wake-up on change occurs and the pins are not read before reentering sleep, a wake-up will occur immediately even if no pins change while in sleep mode. note 1: caution: right before entering sleep, read the comparator configuration register(s) cm1con0 and cm2con0. when in sleep, wake-up occurs when the comparator output bit c1out and c2out change from the state they were in at the last reading. if a wake-up on comparator change occurs and the pins are not read before re-entering sleep, a wake-up will occur immediately, even if no pins change while in sleep mode. 2: for 16f506 only.
pic12f510/16f506 ds41268d-page 70 ? 2007 microchip technology inc. 10.12 in-circuit serial programming? (icsp?) the pic12f510/16f506 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manu- facture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware, or a custom firmware, to be programmed. the devices are placed into a program/verify mode by holding the gp1/rb1 and gp0/rb0 pins low while rais- ing the mclr (v pp ) pin from v il to v ihh (see program- ming specification). gp1/rb1 becomes the programming clock and gp0/rb0 becomes the programming data. both gp1/rb1 and gp0/rb0 are schmitt trigger inputs in this mode. after reset, a 6-bit command is supplied to the device. depending on the command and if the command was a load or a read, 14 bits of program data are then sup- plied to or from the device. for complete details of serial programming, please refer to the pic12f510/16f506 programming specifications. a typical in-circuit serial programming connection is shown in figure 10-15. figure 10-15: typical in-circuit serial programming connection external connector signals to n o r m a l connections to n o r m a l connections pic12f510 v dd v ss mclr /v pp gp1/rb1 gp0/rb0 +5v 0v v pp clk data i/o v dd pic16f506
? 2007 microchip technology inc. ds41268d-page 71 pic12f510/16f506 11.0 instruction set summary the pic16 instruction set is highly orthogonal and is comprised of three basic categories. ? byte-oriented operations ? bit-oriented operations ? literal and control operations each pic16 instruction is a 12-bit word divided into an opcode , which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the formats for each of the catego- ries is presented in figure 11-1, while the various opcode fields are summarized in table 11-1. for byte-oriented instructions, ?f? represents a file register designator and ?d? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator which selects the number of the bits affected by the operation, while ?f? represents the number of the file in which the bit is located. for literal and control operations, ?k? represents an 8 or 9-bit constant or literal value. table 11-1: opcode field descriptions all instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. figure 11-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal number: 0xhhh where ?h? signifies a hexadecimal digit. figure 11-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ) the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register ?f?) default is d = 1 label label name tos top-of-stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents assigned to < > register bit field in the set of italics user defined term (font is courier) byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit file register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations ? goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value
pic12f510/16f506 ds41268d-page 72 ? 2007 microchip technology inc. table 11-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc, z z z z z z none z none z z none none c c c, dc, z none z 1, 2, 4 2, 4 4 2, 4 2, 4 2, 4 2, 4 2, 4 2, 4 1, 4 2, 4 2, 4 1, 2, 4 2, 4 2, 4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2, 4 2, 4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k ? k k k ? k ? f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none to , pd none z none none none to , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a ? 0 ? by any instruction that writes to the pc except for goto . see section 4.6 ?program counter? . 2: when an i/o register is modified as a function of itself (e.g. movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 3: the instruction tris f , where f = 6, causes the contents of the w register to be written to the tri-state latches of portb. a ? 1 ? forces the pin to a high-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared (if assigned to tmr0).
? 2007 microchip technology inc. ds41268d-page 73 pic12f510/16f506 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 31 d [ 0 , 1 ] operation: (w) + (f) (dest) status affected: c, dc, z description: add the contents of the w register and register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) (w) status affected: z description: the contents of the w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 31 d [0,1] operation: (w) .and. (f) (dest) status affected: z description: the contents of the w register are and?ed with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 31 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 31 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 31 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruc- tion fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two-cycle instruction.
pic12f510/16f506 ds41268d-page 74 ? 2007 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 31 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruc- tion fetched during the current instruction execution, is discarded and a nop is executed instead, making this a two-cycle instruction. call subroutine call syntax: [ label ] call k operands: 0 k 255 operation: (pc) + 1 top-of-stack; k pc<7:0>; (status <6:5>) pc<10:9>; 0 pc<8> status affected: none description: subroutine call. first, return address (pc + 1) is pushed onto the stack. the eight-bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from status <6:5>, pc<8> is cleared. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 31 operation: 00h (f); 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w); 1 z status affected: z description: the w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt; 0 wdt prescaler (if assigned); 1 to; 1 pd status affected: to , pd description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 f 31 d [0,1] operation: (f ) (dest) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2007 microchip technology inc. ds41268d-page 75 pic12f510/16f506 decf decrement f syntax: [ label ] decf f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 (dest) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 d; skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, the next instruc- tion, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 511 operation: k pc<8:0>; status <6:5> pc<10:9> status affected: none description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status <6:5>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, then the next instruction, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. (k) (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register.
pic12f510/16f506 ds41268d-page 76 ? 2007 microchip technology inc. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 31 d [0,1] operation: (w).or. (f) (dest) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. movf move f syntax: [ label ] movf f,d operands: 0 f 31 d [0,1] operation: (f) (dest) status affected: z description: the contents of register ?f? are moved to destination ?d?. if ?d? is ? 0 ?, destination is the w register. if ?d? is ? 1 ?, the destination is file register ?f?. ?d? = 1 is useful as a test of a file register, since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight-bit literal ?k? is loaded into the w register. the ?don?t cares? will be assembled as ? 0 ?s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 31 operation: (w) (f) status affected: none description: move data from the w register to register ?f?. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. option load option register syntax: [ label ] option operands: none operation: (w) option status affected: none description: the content of the w register is loaded into the option register.
? 2007 microchip technology inc. ds41268d-page 77 pic12f510/16f506 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. c register ?f? c register ?f? sleep enter sleep mode syntax: [ label ]sleep operands: none operation: 00h wdt; 0 wdt prescaler; 1 to ; 0 pd status affected: to , pd, rbwuf description: time-out status bit (to ) is set. the power-down status bit (pd ) is cleared. rbwuf is unaffected. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 10.9 ?power-down mode (sleep)? on sleep for more details. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 31 d [0,1] operation: (f) ? (w) ( dest) status affected: c, dc, z description: subtract (2?s complement method) the w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 31 d [0,1] operation: (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w register. if ?d? is ? 1 ?, the result is placed in register ?f?.
pic12f510/16f506 ds41268d-page 78 ? 2007 microchip technology inc. tris load tris register syntax: [ label ] tris f operands: f = 6 operation: (w) tris register f status affected: none description: tris register ?f? (f = 6 or 7) is loaded with the contents of the w register xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 31 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2007 microchip technology inc. ds41268d-page 79 pic12f510/16f506 12.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab real ice? in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 12.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic12f510/16f506 ds41268d-page 80 ? 2007 microchip technology inc. 12.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 12.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 and pic24 families of microcontrol- lers and the dspic30 and dspic33 family of digital sig- nal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 12.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 12.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 12.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
? 2007 microchip technology inc. ds41268d-page 81 pic12f510/16f506 12.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 12.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc ? and mcu devices. it debugs and programs pic ? and dspic ? flash microcontrollers with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the mplab real ice probe is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with the popular mplab icd 2 system (rj11) or with the new high speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). mplab real ice is field upgradeable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 12.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost- effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected pic devices. 12.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications.
pic12f510/16f506 ds41268d-page 82 ? 2007 microchip technology inc. 12.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 12.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer and selected flash device debugger with an easy-to-use interface for programming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping development board, twelve sequential lessons, software and hi-tech?s picc? lite c compiler, and is designed to help get up to speed quickly using pic ? microcontrollers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 12.13 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart ? battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) and the latest ?product selector guide? (ds00148) for the complete list of demonstration, development and evaluation kits.
? 2007 microchip technology inc. ds41268d-page 83 pic12f510/16f506 13.0 electrical characteristics absolute maximum ratings? ambient temperature under bias................................................................................................. ......... -40c to +125c storage temperature ............................................................................................................ ................ -65c to +150c voltage on v dd with respect to v ss ............................................................................................................... 0 to +7.0v voltage on mclr with respect to v ss .............................................................................................................0 to +14v voltage on all other pins with respect to v ss ............................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... ... 700 mw max. current out of v ss pin ........................................................................................................................... ..... 200 ma max. current into v dd pin ........................................................................................................................... ........ 150 ma input clamp current, i ik (v i < 0 or v i > v dd ) ................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ........................................................................................................... 20 ma max. output current sunk by any i/o pin ........................................................................................ ...................... 25 ma max. output current sourced by any i/o pin ..................................................................................... .................... 25 ma max. output current sourced by i/o port ....................................................................................... ..................... 100 ma max. output current sunk by i/o port .......................................................................................... ....................... 100 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic12f510/16f506 ds41268d-page 84 ? 2007 microchip technology inc. figure 13-1: voltage-frequency graph, -40 c t a +125 c (pic12f510) figure 13-2: maximum oscillator frequency table (pic12f510) 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 8 0 200 khz 4 mhz frequency (mhz) 8mhz 20mhz lp xt extrc intosc oscillator mode
? 2007 microchip technology inc. ds41268d-page 85 pic12f510/16f506 figure 13-3: voltage frequency graph, -40 c t a +125 c (pic16f506) figure 13-4: maximum oscillator frequency table (pic16f506) 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 8 0 200 khz 4 mhz frequency (mhz) 8mhz 20mhz lp xt extrc intosc ec hs oscillator mode
pic12f510/16f506 ds41268d-page 86 ? 2007 microchip technology inc. 13.1 dc characteristics: pic12f510/16f506 (industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 40 c t a +85 c (industrial) param no. sym characteristic min typ (1) max units conditions d001 v dd supply voltage 2.0 5.5 v see figure 14-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?vss? vsee section 10.4 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 10.4 ?power-on reset (por)? for details d010 i dd supply current (3,4) ? ? 175 0.625 275 1.1 a ma f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v ? ? 250 1.0 450 1.5 a ma f osc = 8 mhz, v dd = 2.0v f osc = 8 mhz, v dd = 5.0v ?1.42.0maf osc = 20 mhz, v dd = 5.0v ? ? 11 38 15 52 a a f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 5.0v d020 i pd power-down current (5) ? ? 0.1 0.35 1.2 2.4 a a v dd = 2.0v v dd = 5.0v d022 i wdt wdt current (5) ? ? 1.0 7.0 3.0 16.0 a a v dd = 2.0v v dd = 5.0v d023 icmp comparator current (5) ? ? 15 55 22 67 a a v dd = 2.0v (per comparator) v dd = 5.0v (per comparator) d022 i cvref cv ref current (5) ? ? 30 75 60 125 a a v dd = 2.0v (high range) v dd = 5.0v (high range) d023 i fvr internal 0.6v fixed voltage reference current (5) ? ? 85 175 120 205 a a v dd = 2.0v (0.6v reference and 1 comparator enabled) v dd = 5.0v (0.6v reference and 1 comparator enabled) d024 i ad a/d conversion current (5) ? 120 150 a2.0v ? 200 250 a5.0v * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 5: for standby current measurements, the conditions are the same as i dd , except that the device is in sleep mode. if a module current is listed, the current is for that specific module enabled and the device in sleep. 6: does not include current through r ext . the current through the resistor can be estimated by the formula: i = v dd /2r ext (ma) with r ext in k .
? 2007 microchip technology inc. ds41268d-page 87 pic12f510/16f506 13.2 dc characteristics: pic12f510/16f506 (extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 40 c t a +125 c (extended) param no. sym characteristic min typ (1) max units conditions d001 v dd supply voltage 2.0 5.5 v see figure 14-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?vss? vsee section 10.4 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 10.4 ?power-on reset (por)? for details d010 i dd supply current (3,4) ? ? 175 0.625 275 1.1 a ma f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v ? ? 250 1.0 450 1.5 a ma f osc = 8 mhz, v dd = 2.0v f osc = 8 mhz, v dd = 5.0v ?1.42.0maf osc = 20 mhz, v dd = 5.0v ? ? 11 38 16 54 a a f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 5.0v d020 i pd power-down current (5) ? ? 0.1 0.35 9.0 15.0 a a v dd = 2.0v v dd = 5.0v d022 i wdt wdt current (5) ? ? 1.0 7.0 18 22 a a v dd = 2.0v v dd = 5.0v d023 icmp comparator current (5) ? ? 15 55 25 75 a a v dd = 2.0v (per comparator) v dd = 5.0v (per comparator) d022 i cvref cv ref current (5) ? ? 30 75 65 135 a a v dd = 2.0v (high range) v dd = 5.0v (high range) d023 i fvr internal 0.6v fixed voltage reference current (5) ? ? 85 175 130 220 a a v dd = 2.0v (0.6v reference and 1 comparator enabled) v dd = 5.0v (0.6v reference and 1 comparator enabled) d024 i ad a/d conversion current (5) ? 120 150 a2.0v ? 200 250 a5.0v * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 5: for standby current measurements, the conditions are the same as i dd , except that the device is in sleep mode. if a module current is listed, the current is for that specific module enabled and the device in sleep. 6: does not include current through r ext . the current through the resistor can be estimated by the formula: i = v dd /2r ext (ma) with r ext in k .
pic12f510/16f506 ds41268d-page 88 ? 2007 microchip technology inc. 13.3 dc characteristics: pic12f510/16f506 (industrial, extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40c t a +85c (industrial) -40c t a +125c (extended) param no. sym characteristic min typ? max units conditions v il input low voltage i/o ports d030 with ttl buffer v ss ?0.8v vfor 4.5 v dd 5.5v d030a v ss ?0.15v dd v otherwise d031 with schmitt trigger buffer v ss ?0.15v dd v d032 mclr , t0cki v ss ?0.15v dd v d033 osc1 (in extrc), ec (1) v ss ?0.15 v dd v d033 osc1 (in hs) v ss ?0.3v dd v d033 osc1 (in xt and lp) v ss ?0.3 v dd v v ih input high voltage i/o ports ? d040 with ttl buffer 2.0 ? v dd v4.5 v dd 5.5v d040a 0.25 v dd ?v dd v otherwise + 0.8v d041 with schmitt trigger buffer 0.85 v dd ?v dd v for entire v dd range d042 mclr , t0cki 0.85 v dd ?v dd v d043 osc1 (in extrc), ec (1) 0.85 v dd ?v dd v d043 osc1 (in hs) 0.7 v dd ?v dd v d043 osc1 (in xt and lp) 1.6 ? v dd v d070 i pur gpio/portb weak pull-up current 50 250 400 av dd = 5v, v pin = v ss i il input leakage current (2), (3) d060 i/o ports ? ? 1 av ss v pin v dd , pin at high-impedance d062 gp3/rb3/mclr (5) 50 250 400 av dd = 5v d061a gp3/rb3/mclr (4) ?+0.75 av ss v pin v dd d063 osc1 ? ? 5 av ss v pin v dd , xt, hs and lp oscillator configuration output low voltage d080 v ol i/o ports/clkout ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, ?40 c to +85 c d080a ? ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, ?40 c to +125 c d083 osc2 ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v, ?40 c to +85 c d083a ? ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, ?40 c to +125 c output high voltage d090 v oh i/o ports/clkout (3) v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, ?40 c to +85 c d090a v dd ? 0.7 ? ? v i oh = -2.5 ma, v dd = 4.5v, ?40 c to +125 c d092 osc2 v dd ? 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, ?40 c to +85 c d092a v dd ? 0.7 ? ? v i oh = -1.0 ma, v dd = 4.5v, ?40 c to +125 c capacitive loading specs on output pins d100 c osc 2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 c io all i/o pins ? ? 50 pf ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic12f510/16f5 06 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: this specification applies when gp3/mclr is configured as an input with the pull-up disabled. the leakage current for the gp3/rb3/ mclr pin is higher than for the standard i/o port pins. 5: this specification applies when gp3/rb3/mclr is configured as the mclr reset pin function with the weak pull-up always enabled.
? 2007 microchip technology inc. ds41268d-page 89 pic12f510/16f506 table 13-1: comparator specifications table 13-2: comparator voltage reference (cv ref ) specifications table 13-3: a/d converter character istics (pic16f506/pic12f510) sym characteristics min typ max units comments v os input offset voltage ? 3 10 mv (v dd - 1.5v)/2 v cm input common mode voltage 0 ? v dd ? 1.5 v c mrr common mode rejection ratio +55* ? ? db t rt response time (1) ? 150 400* ns internal v ivrf internal voltage reference 0.550 0.6 0.650 v * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd ? 1.5v. sym characteristics min typ max units comments cv res resolution ? ? v dd /24* v dd /32 ? ? lsb lsb low range (v rr = 1 ) high range (v rr = 0 ) absolute accuracy ? ? ? ? 1/2* 1/2* lsb lsb low range (v rr = 1 ) high range (v rr = 0 ) unit resistor value (r) ? ? 2k* ? settling time (1) ??10* s * these parameters are characterized but not tested. note 1: settling time measured while v rr = 1 and vr<3:0> transitions from 0000 to 1111 . param no. sym characteristic min typ? max units conditions a01 n r resolution ? ? 8 bits bit a03 e il integral error ? ? 1.5 lsb v dd = 5.0v a04 e dl differential error ? ? -1 < e dl 1.5 lsb no missing codes to 8 bits v dd = 5.0v a05 e fs full-scale range 2 ? 5.5* v v dd a06 e off offset error ? ? 1.5 lsb v dd = 5.0v a07 e gn gain error -0.5 ? +1.75 lsb v dd = 5.0v a10 ? monotonicity ? guaranteed (1) ??v ss v ain v dd a25 v ain analog input voltage v ss ?v dd v a30 z ain recommended impedance of analog voltage source ?? 10 k * these parameters are characterized but not tested. ? data in the ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only are not tested. note 1: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
pic12f510/16f506 ds41268d-page 90 ? 2007 microchip technology inc. 13.4 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: figure 13-5: load conditions figure 13-6: extern al clock timing 1. tpps2pps 2. tpps t f frequency t time lowercase (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance cl v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1 legend: osc1 q4 q1 q2 q3 q4 q1 133 44 2
? 2007 microchip technology inc. ds41268d-page 91 pic12f510/16f506 table 13-4: external clock timing requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial), -40 c t a +125 c (extended) para no. sym characteristic min typ (1) max units conditions 1a f osc external clkin frequency (2) dc ? 4 mhz xt oscillator mode dc ? 20 mhz hs/ec oscillator mode (pic16f506 only) dc ? 200 khz lp oscillator mode oscillator frequency (2) ? ? 4 mhz extrc oscillator mode 0.1 ? 4 mhz xt oscillator mode 4 ? 20 mhz hs/ec oscillator mode (pic16f506 only) ? ? 200 khz lp oscillator mode 1t osc external clkin period (2) 250 ? ? ns xt oscillator mode 50 ? ? ns hs/ec oscillator mode (pic16f506 only) 5? ? s lp oscillator mode oscillator period (2) 250 ? ? ns extrc oscillator mode 250 ? 10,000 ns xt oscillator mode 50 ? 250 ns hs/ec oscillator mode (pic16f506 only) 5? ? s lp oscillator mode 2t cy instruction cycle time 200 4/f osc ?ns 3tosl, to s h clock in (osc1) low or high time 50* ? ? ns xt oscillator 2* ? ? s lp oscillator 10 ? ? ns hs/ec oscillator (pic16f506 only) 4tosr, to s f clock in (osc1) rise or fall time ? ? 25* ns xt oscillator ? ? 50* ns lp oscillator ? ? 15 ns hs/ec oscillator (pic16f506 only) * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices.
pic12f510/16f506 ds41268d-page 92 ? 2007 microchip technology inc. table 13-5: calibrated internal rc frequencies figure 13-7: i/o timing ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial), -40 c t a +125 c (extended) param no. sym characteristic freq. tolerance min typ (1) max* units conditions f10 f osc internal calibrated intosc frequency (1) 1% 2% 5% 7.92 7.84 7.60 8.00 8.00 8.00 8.08 8.16 8.40 mhz mhz mhz v dd = 3.5v t a = 25c 2.5v v dd 5.5v 0c t a +85c 2.0v v dd 5.5v -40c t a +85c (ind.) -40c t a +125c (ext.) * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. osc1 i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 18 old value new value 19 note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout.
? 2007 microchip technology inc. ds41268d-page 93 pic12f510/16f506 table 13-6: timing requirements figure 13-8: reset, watchdog timer and device reset timer timing ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) -40 c t a +125 c (extended) param no. sym characteristic min typ (1) max units 17 t os h2 io vosc1 (q1 cycle) to port out valid (2), (3) ? ? 100* ns 18 t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) (2) 50 ? ? ns 19 t io v2 os h port input valid to osc1 (i/o in setup time) 20 ? ? ns 20 t io r port output rise time (2), (3) ? 10 25** ns 21 t io f port output fall time (2), (3) ? 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in extrc mode. 3: see figure 13-5 for loading conditions. v dd mclr internal por drt timeout (2) internal reset watchdog timer reset 32 31 34 i/o pin (1) 32 32 34 30 note 1: i/o pins must be taken out of high-impedance mode by enabling the output drivers in software. 2: runs in mclr or wdt reset only in xt, lp and hs modes.
pic12f510/16f506 ds41268d-page 94 ? 2007 microchip technology inc. table 13-7: reset, watchdog timer and device reset timer figure 13-9: timer0 clock timings table 13-8: timer0 clock requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) -40 c t a +125 c (extended) param no. sym characteristic min typ (1) max units conditions 30 t mc lmclr pulse width (low) 2000* ? ? ns v dd = 5.0v 31 t wdt watchdog timer time-out period (no prescaler) 9* 9* 18* 18* 30* 40* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 32 t drt device reset timer period standard 9* 9* 18* 18* 30* 40* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) short 0.5* 0.5* 1.125* 1.125* 2* 2.5* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 34 t ioz i/o high-impedance from mclr low ? ? 2000* ns * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) -40 c t a +125 c (extended) parm no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40* n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
? 2007 microchip technology inc. ds41268d-page 95 pic12f510/16f506 table 13-9: pull-up resistor ranges v dd (volts) temperature ( c) min typ max units rb0 (gp0)/rb1 (gp1) 2.0 -40 73k 105k 186k 25 73k 113k 187k 85 82k 123k 190k 125 86k 132k 190k 5.5 -40 15k 21k 33k 25 15k 22k 34k 85 19k 26k 35k 125 23k 29k 35k rb3 (gp3) 2.0 -40 63k 81k 96k 25 77k 93k 116k 85 82k 96k 116k 125 86k 100k 119k 5.5 -40 16k 20k 22k 25 16k 21k 23k 85 24k 25k 28k 125 26k 27k 29k
pic12f510/16f506 ds41268d-page 96 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds41268d-page 97 pic12f510/16f506 14.0 dc and characteristics graphs and charts . ?typical? represents the mean of the distribution at 25 c. ?maximum? or ?minimum? represents (mean + 3 ) or (mean - 3 ) respectively, where s is a standard deviation, over each temperature range. figure 14-1: i dd vs. v dd over f osc note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. xt mode 0 200 400 600 800 1,000 1,200 1,400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 4 mhz 4 mhz maximum typical
pic12f510/16f506 ds41268d-page 98 ? 2007 microchip technology inc. figure 14-2: typical i pd vs. v dd (sleep mode, all peripherals disabled) figure 14-3: maximum i pd vs. v dd (sleep mode, all peripherals disabled) typical (sleep mode all peripherals disabled) 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) maximum (sleep mode all peripherals disabled) max. 125c max. 85c 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 2.02.5 3.03.5 4.04.5 5.05.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2007 microchip technology inc. ds41268d-page 99 pic12f510/16f506 figure 14-4: comparator i pd vs. v dd (comparator enabled) figure 14-5: typical wdt i pd vs. v dd 0 20 40 60 80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) typical maximum 0 1 2 3 4 5 6 7 8 9 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
pic12f510/16f506 ds41268d-page 100 ? 2007 microchip technology inc. figure 14-6: maximum wdt i pd vs. v dd over temperature figure 14-7: wdt time-out vs. v dd over temperature (no prescaler) m ax i mum max. 125c max. 85c 0.0 5.0 10.0 15.0 20.0 25.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 0 5 10 15 20 25 30 35 40 45 50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) time (ms) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) max. 125c max. 85c typical. 25c min. -40c
? 2007 microchip technology inc. ds41268d-page 101 pic12f510/16f506 figure 14-8: v ol vs. i ol over temperature (v dd = 3.0v) figure 14-9: v ol vs. i ol over temperature (v dd = 5.0v) (vdd = 3v , - 40 c to 125 c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 i ol (ma) v ol (v) max. 85c max. 125c typical 25c min. -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 i ol (ma) v ol (v) typical: statistical mean @25c maximum: meas + 3 (-40c to 125c) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) max. 85c typ. 25c min. -40c max. 125c
pic12f510/16f506 ds41268d-page 102 ? 2007 microchip technology inc. figure 14-10: v oh vs. i oh over temperature (v dd = 3.0v) figure 14-11: v oh vs. i oh over temperature (v dd = 5.0v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 i oh (ma) v oh (v) typ. 25c max. -40c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) (, ) 3.0 3.5 4.0 4.5 5.0 5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 i oh (ma) v oh (v) max. -40c typ. 25c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2007 microchip technology inc. ds41268d-page 103 pic12f510/16f506 figure 14-12: ttl input threshold v in vs. v dd figure 14-13: schmitt trigger input threshold v in vs. v dd (ttl input, -40c to 125c) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) typ. 25c max. -40c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) (st i npu t , - 40 c to 125 c) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max. 125c v ih min. -40c v il min. 125c v il max. -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
pic12f510/16f506 ds41268d-page 104 ? 2007 microchip technology inc. figure 14-14: device reset timer (hs, xt and lp) vs. v dd maximum (sleep mode all peripherals disabled) 0 5 10 15 20 25 30 35 40 45 2.02.5 3.03.5 4.04.5 5.05.5 v dd (v) drt (ms) min. -40c max. 125c typical 25c max. 85c note: see table 13-7 if another clock mode is selected.
? 2007 microchip technology inc. ds41268d-page 105 pic12f510/16f506 15.0 packaging 15.1 package marking information xxxxxnnn 8-lead pdip xxxxxxxx yyww 017 example 12f510/p 0410 14-lead pdip xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn example pic16f506-i/p 0410017 8-lead soic (3.90 mm) xxxxxxxx xxxxyyww nnn example pic12f510-i /sn0410 017 x x x y w w n n 8-lead 2x3 dfn* b e 0 6 1 0 1 7 example * standard pic ? device marking consists of microchip part number, year code, week code and traceability code. for pic device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e table 15-1: 8-lead 2x3 dfn (mc) top marking part number marking pic12f510(t)-i/mc bs0 pic12f510-e/mc bt0
pic12f510/16f506 ds41268d-page 106 ? 2007 microchip technology inc. 15.2 package marking information (cont?d) 8-lead msop xxxxxx ywwnnn example 602/ms 310017 14-lead tssop (4.4 mm) xxxxxxxx yyww nnn example 16f506/st 0410 017 14-lead soic (3.90 mm) xxxxxxxxxxx xxxxxxxxxxx yywwnnn example pic16f506 -i/sl 0410017
? 2007 microchip technology inc. ds41268d-page 107 pic12f510/16f506

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? 2007 microchip technology inc. ds41268d-page 115 pic12f510/16f506 appendix a: revision history revision a original release. revision b page 3 ? special microcontroller features and low- power features sections. pic12f510 pin diagram. section 3.0 ? figure 3-1, figure 3-2, table 3-2, table 3-3. section 4.0 ? first paragraph, section 4.2 - figure references, tables 4-1 and 4-2 (note 1). section 5.0 ? table 5-2, table 5-6 title. section 6.0 section 7.0 ? first paragraph, section 7.7, register 7-1, register 7-2, register 7-3, figure 7-1, figure 7-2, sections 7.4 through 7.7, table 7-1. section 8.0 ? sections 8.0 through 8.2, figure 8-1, table 8-1. section 9.0 ? table 9-2, register 9-1, register 9-2, table 9-3. section 10.0 ? registers 10-1 and 10-2 (note 1), table 10-2 (note 2), section 10.2.5, section 10.3, table 10-3, table 10-4, table 10-5, section 10.4, section 10.5, section 10.6.1, section 10.9, 10.9.1, 10.9.2, section 10.11. section 13.0 ? 13.1 dc characteristics, 13.2 dc characteristics, table 13-1, table 13-3, table 13-4. revision c (03/2007) revised table 3-2 gp3 and legend; revised table 3- 3 rb3 and legend; updated registers to new format; revised section 9.1; revised table 9-2; revised 13.1 dc characteristics d025; revised table 13-2 and table 13-3 and notes; replaced package drawings (rev. an); added dfn package; replaced develop- ment support section; revised product id system. revision d (11/2007) revised table 1-1; table 4-1, table 4-2; figure 4-5; register 7-1 (note 1); register 8-1; figure 13-4; 13.1 - 13.3; table 13-1, table 13-3, table 13-6, table 13-7, table 13-9; figure 14-4, figure 14-14; section 14.0; packaging; product id system.
pic12f510/16f506 ds41268d-page 116 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds41268d-page 117 pic12f510/16f506 index a alu ....................................................................................... 9 assembler mpasm assembler..................................................... 80 b block diagram comparator for the pic12f510................................... 46 comparator for the pic16f506................................... 46 on-chip reset circuit ................................................. 64 timer0......................................................................... 39 tmr0/wdt prescaler................................................. 42 watchdog timer.......................................................... 67 brown-out protection circuit .............................................. 68 c c compilers mplab c18 ................................................................ 80 mplab c30 ................................................................ 80 carry ..................................................................................... 9 clocking scheme ................................................................ 14 code protection ............................................................ 55, 69 configuration bits................................................................ 55 configuration word (pic12f510) ....................................... 56 configuration word (pic16f506) ....................................... 57 customer change notification service ............................. 108 customer notification service........................................... 108 customer support............................................................. 108 d dc ....................................................................................... 88 dc characteristics (extended) ........................................... 87 dc characteristics (industrial) ............................................ 86 dc characteristics (industrial, extended) ........................... 88 development support ......................................................... 79 digit carry ............................................................................. 9 e errata .................................................................................... 3 f family of devices pic12f510/16f506....................................................... 5 fsr ..................................................................................... 24 i i/o interfacing ..................................................................... 27 i/o ports .............................................................................. 27 i/o programming considerations........................................ 37 id locations .................................................................. 55, 69 indf.................................................................................... 24 indirect data addressing..................................................... 24 instruction cycle ................................................................. 14 instruction flow/pipelining .................................................. 14 instruction set summary..................................................... 72 internet address................................................................ 108 l loading of pc ..................................................................... 23 m memory organization ......................................................... 15 data memory .............................................................. 16 program memory (pic12f510/16f506) ..................... 15 microchip internet web site.............................................. 108 mplab asm30 assembler, linker, librarian ..................... 80 mplab icd 2 in-circuit debugger ..................................... 81 mplab ice 2000 high-performance universal in-circuit emulator...................................................... 81 mplab ice 4000 high-performance universal in-circuit emulator...................................................... 81 mplab integrated development environment software.... 79 mplab pm3 device programmer ...................................... 81 mplink object linker/mplib object librarian .................. 80 o option register................................................................ 20 osc selection .................................................................... 55 osccal register............................................................... 22 oscillator configurations..................................................... 58 oscillator types hs............................................................................... 58 lp ............................................................................... 58 rc .............................................................................. 58 xt ............................................................................... 58 p pic12f510/16f506 device varieties ................................... 7 picstart plus development programmer....................... 82 por device reset timer (drt) ................................... 55, 66 pd ............................................................................... 68 power-on reset (por)............................................... 55 to ............................................................................... 68 portb ............................................................................... 27 power-down mode.............................................................. 69 prescaler ............................................................................ 41 program counter ................................................................ 23 q q cycles .............................................................................. 14 r rc oscillator....................................................................... 59 reader response............................................................. 109 read-modify-write.............................................................. 37 register file map pic12f510 ................................................................. 16 pic16f506 ................................................................. 16 registers special function ......................................................... 17 reset .................................................................................. 55 reset on brown-out ........................................................... 68 s sleep ............................................................................ 55, 69 software simulator (mplab sim) ...................................... 80 special features of the cpu .............................................. 55 special function registers ................................................. 17 stack................................................................................... 23 status register ..................................................... 9, 18, 51
pic12f510/16f506 ds41268d-page 118 ? 2007 microchip technology inc. t timer0 timer0 ......................................................................... 39 timer0 (tmr0) module ............................................... 39 tmr0 with external clock........................................... 41 timing diagrams and specifications................................... 91 timing parameter symbology and load conditions........... 91 tris registers.................................................................... 27 w wake-up from sleep ........................................................... 69 watchdog timer (wdt) ................................................ 55, 66 period.......................................................................... 66 programming considerations ..................................... 66 www address.................................................................. 108 www, on-line support........................................................ 3 z zero bit .................................................................................. 9
? 2007 microchip technology inc. ds41268d-page 119 pic12f510/16f506 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic12f510/16f506 ds41268d-page 120 ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41268d pic12f510/16f506 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2007 microchip technology inc. ds41268d-page 121 pic12f510/16f506 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f506 pic12f510 pic16f506t (1) pic12f510t (2) v dd range 2.0v to 5.5v temperature range: i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package: mc = 8l dfn 2x3 (dual flatpack no-leads) (3, 4) ms = micro-small outline package (msop) (3, 4) p = plastic (pdip) (4) sl = 14l small outline, 3.90 mm (soic) (4) sn = 8l small outline, 3.90 mm narrow (soic) (4) st = thin shrink small outline (tssop) (4) pattern: qtp, sqtp code or special requirements (blank otherwise) examples: a) pic16f506-e/p 301 = extended temp., pdip package, qtp pattern #301 b) pic16f506-i/sn = industrial temp., soic package c) pic16f506t-e/p = extended temp., pdip package, tape and reel note 1: t = in tape and reel soic and tssop packages only 2: t = in tape and reel soic and msop packages only. 3: pic12f510 only. 4: pb-free.
ds41268d-page 122 ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 10/05/07

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